Document Outline

• IA-32 Intel® Architecture Optimization Reference Manual
• Disclaimer
• Contents
• Introduction
• 1 IA-32 Intel® Architecture Processor Family Overview
  • SIMD Technology
    • Summary of SIMD Technologies
      • MMX™ Technology
      • Streaming SIMD Extensions
      • Streaming SIMD Extensions 2
      • Streaming SIMD Extensions 3
  • Intel® Extended Memory 64 Technology (Intel® EM64T)
  • Intel NetBurst® Microarchitecture
    • Design Goals of Intel NetBurst Microarchitecture
    • Overview of the Intel NetBurst Microarchitecture Pipeline
      • The Front End
      • The Out-of-order Core
      • Retirement
    • Front End Pipeline Detail
      • Prefetching
      • Decoder
      • Execution Trace Cache
      • Branch Prediction
    • Execution Core Detail
      • Instruction Latency and Throughput
      • Execution Units and Issue Ports
      • Caches
      • Data Prefetch
      • Loads and Stores
      • Store Forwarding
  • Intel® Pentium® M Processor Microarchitecture
    • The Front End
    • Data Prefetching
    • Out-of-Order Core
    • In-Order Retirement
  • Microarchitecture of Intel® Core™ Solo and Intel® Core™ Duo Processors
    • Front End
    • Data Prefetching
  • Hyper-Threading Technology
    • Processor Resources and Hyper-Threading Technology
      • Replicated Resources
      • Partitioned Resources
      • Shared Resources
    • Microarchitecture Pipeline and Hyper-Threading Technology
    • Front End Pipeline
    • Execution Core
    • Retirement
  • Multi-Core Processors
    • Microarchitecture Pipeline and Multi-Core Processors
    • Shared Cache in Intel Core Duo Processors
      • Load and Store Operations
• 2 General Optimization Guidelines
  • Tuning to Achieve Optimum Performance
  • Tuning to Prevent Known Coding Pitfalls
  • General Practices and Coding Guidelines
    • Use Available Performance Tools
    • Optimize Performance Across Processor Generations
    • Optimize Branch Predictability
    • Optimize Memory Access
    • Optimize Floating-point Performance
    • Optimize Instruction Selection
    • Optimize Instruction Scheduling
    • Enable Vectorization
  • Coding Rules, Suggestions and Tuning Hints
  • Performance Tools
    • Intel® C++ Compiler
    • General Compiler Recommendations
    • VTune™ Performance Analyzer
  • Processor Perspectives
    • CPUID Dispatch Strategy and Compatible Code Strategy
    • Transparent Cache-Parameter Strategy
    • Threading Strategy and Hardware Multi-Threading Support
  • Branch Prediction
    • Eliminating Branches
    • Spin-Wait and Idle Loops
    • Static Prediction
    • Inlining, Calls and Returns
    • Branch Type Selection
    • Loop Unrolling
    • Compiler Support for Branch Prediction
  • Memory Accesses
    • Alignment
    • Store Forwarding
      • Store-to-Load-Forwarding Restriction on Size and Alignment
      • Store-forwarding Restriction on Data Availability
    • Data Layout Optimizations
    • Stack Alignment
    • Capacity Limits and Aliasing in Caches
      • Capacity Limits in Set-Associative Caches
      • Aliasing Cases in the Pentium® 4 and Intel® Xeon® Processors
      • Aliasing Cases in the Pentium M Processor
    • Mixing Code and Data
      • Self-modifying Code
    • Write Combining
    • Locality Enhancement
    • Minimizing Bus Latency
    • Non-Temporal Store Bus Traffic
    • Prefetching
      • Hardware Instruction Fetching
      • Software and Hardware Cache Line Fetching
    • Cacheability Instructions
    • Code Alignment
  • Improving the Performance of Floating-point Applications
    • Guidelines for Optimizing Floating-point Code
    • Floating-point Modes and Exceptions
      • Floating-point Exceptions
      • Floating-point Modes
    • Improving Parallelism and the Use of FXCH
    • x87 vs. Scalar SIMD Floating-point Trade-offs
      • Scalar SSE/SSE2 Performance on Intel Core Solo and Intel Core Duo Processors
    • Memory Operands
    • Floating-Point Stalls
      • x87 Floating-point Operations with Integer Operands
      • x87 Floating-point Comparison Instructions
      • Transcendental Functions
  • Instruction Selection
    • Complex Instructions
    • Use of the lea Instruction
    • Use of the inc and dec Instructions
    • Use of the shift and rotate Instructions
    • Flag Register Accesses
    • Integer Divide
    • Operand Sizes and Partial Register Accesses
    • Prefixes and Instruction Decoding
    • REP Prefix and Data Movement
    • Address Calculations
    • Clearing Registers
    • Compares
    • Floating Point/SIMD Operands
    • Prolog Sequences
    • Code Sequences that Operate on Memory Operands
  • Instruction Scheduling
    • Latencies and Resource Constraints
    • Spill Scheduling
    • Scheduling Rules for the Pentium 4 Processor Decoder
    • Scheduling Rules for the Pentium M Processor Decoder
  • Vectorization
  • Miscellaneous
    • NOPs
  • Summary of Rules and Suggestions
    • User/Source Coding Rules
    • Assembly/Compiler Coding Rules
    • Tuning Suggestions
• 3 Coding for SIMD Architectures
  • Checking for Processor Support of SIMD Technologies
    • Checking for MMX Technology Support
    • Checking for Streaming SIMD Extensions Support
    • Checking for Streaming SIMD Extensions 2 Support
    • Checking for Streaming SIMD Extensions 3 Support
  • Considerations for Code Conversion to SIMD Programming
    • Identifying Hot Spots
    • Determine If Code Benefits by Conversion to SIMD Execution
  • Coding Techniques
    • Coding Methodologies
      • Assembly
      • Intrinsics
      • Classes
      • Automatic Vectorization
  • Stack and Data Alignment
    • Alignment and Contiguity of Data Access Patterns
      • Using Padding to Align Data
      • Using Arrays to Make Data Contiguous
    • Stack Alignment For 128-bit SIMD Technologies
    • Data Alignment for MMX Technology
    • Data Alignment for 128-bit data
      • Compiler-Supported Alignment
  • Improving Memory Utilization
    • Data Structure Layout
    • Strip Mining
    • Loop Blocking
  • Instruction Selection
    • SIMD Optimizations and Microarchitectures
  • Tuning the Final Application
• 4 Optimizing for SIMD Integer Applications
  • General Rules on SIMD Integer Code
  • Using SIMD Integer with x87 Floating-point
    • Using the EMMS Instruction
    • Guidelines for Using EMMS Instruction
  • Data Alignment
  • Data Movement Coding Techniques
    • Unsigned Unpack
    • Signed Unpack
    • Interleaved Pack with Saturation
    • Interleaved Pack without Saturation
    • Non-Interleaved Unpack
    • Extract Word
    • Insert Word
    • Move Byte Mask to Integer
    • Packed Shuffle Word for 64-bit Registers
    • Packed Shuffle Word for 128-bit Registers
    • Unpacking/interleaving 64-bit Data in 128-bit Registers
    • Data Movement
    • Conversion Instructions
  • Generating Constants
  • Building Blocks
    • Absolute Difference of Unsigned Numbers
    • Absolute Difference of Signed Numbers
    • Absolute Value
    • Clipping to an Arbitrary Range [high, low]
      • Highly Efficient Clipping
      • Clipping to an Arbitrary Unsigned Range [high, low]
    • Packed Max/Min of Signed Word and Unsigned Byte
      • Signed Word
      • Unsigned Byte
    • Packed Multiply High Unsigned
    • Packed Sum of Absolute Differences
    • Packed Average (Byte/Word)
    • Complex Multiply by a Constant
    • Packed 32*32 Multiply
    • Packed 64-bit Add/Subtract
    • 128-bit Shifts
  • Memory Optimizations
    • Partial Memory Accesses
      • Supplemental Techniques for Avoiding Cache Line Splits
    • Increasing Bandwidth of Memory Fills and Video Fills
      • Increasing Memory Bandwidth Using the MOVDQ Instruction
      • Increasing Memory Bandwidth by Loading and Storing to and from the Same DRAM Page
      • Increasing UC and WC Store Bandwidth by Using Aligned Stores
  • Converting from 64-bit to 128-bit SIMD Integer
    • SIMD Optimizations and Microarchitectures
      • Packed SSE2 Integer versus MMX Instructions
• 5 Optimizing for SIMD Floating-point Applications
  • General Rules for SIMD Floating-point Code
  • Planning Considerations
  • Using SIMD Floating-point with x87 Floating-point
  • Scalar Floating-point Code
  • Data Alignment
    • Data Arrangement
      • Vertical versus Horizontal Computation
      • Data Swizzling
      • Data Deswizzling
      • Using MMX Technology Code for Copy or Shuffling Functions
      • Horizontal ADD Using SSE
  • Use of cvttps2pi/cvttss2si Instructions
  • Flush-to-Zero and Denormals-are-Zero Modes
  • SIMD Floating-point Programming Using SSE3
    • SSE3 and Complex Arithmetics
    • SSE3 and Horizontal Computation
    • SIMD Optimizations and Microarchitectures
      • Packed Floating-Point Performance
• 6 Optimizing Cache Usage
  • General Prefetch Coding Guidelines
  • Hardware Prefetching of Data
  • Prefetch and Cacheability Instructions
  • Prefetch
    • Software Data Prefetch
    • The Prefetch Instructions - Pentium 4 Processor Implementation
    • Prefetch and Load Instructions
  • Cacheability Control
    • The Non-temporal Store Instructions
      • Fencing
      • Streaming Non-temporal Stores
      • Memory Type and Non-temporal Stores
      • Write-Combining
    • Streaming Store Usage Models
      • Coherent Requests
      • Non-coherent requests
    • Streaming Store Instruction Descriptions
    • The fence Instructions
      • The sfence Instruction
      • The lfence Instruction
      • The mfence Instruction
    • The clflush Instruction
  • Memory Optimization Using Prefetch
    • Software-controlled Prefetch
    • Hardware Prefetch
    • Example of Effective Latency Reduction with H/W Prefetch
    • Example of Latency Hiding with S/W Prefetch Instruction
    • Software Prefetching Usage Checklist
    • Software Prefetch Scheduling Distance
    • Software Prefetch Concatenation
    • Minimize Number of Software Prefetches
    • Mix Software Prefetch with Computation Instructions
    • Software Prefetch and Cache Blocking Techniques
    • Hardware Prefetching and Cache Blocking Techniques
    • Single-pass versus Multi-pass Execution
  • Memory Optimization using Non-Temporal Stores
    • Non-temporal Stores and Software Write-Combining
    • Cache Management
      • Video Encoder
      • Video Decoder
      • Conclusions from Video Encoder and Decoder Implementation
      • Optimizing Memory Copy Routines
      • TLB Priming
      • Using the 8-byte Streaming Stores and Software Prefetch
      • Using 16-byte Streaming Stores and Hardware Prefetch
      • Performance Comparisons of Memory Copy Routines
  • Deterministic Cache Parameters
    • Cache Sharing Using Deterministic Cache Parameters
    • Cache Sharing in Single-core or Multi-core
    • Determine Prefetch Stride Using Deterministic Cache Parameters
• 7 Multi-Core and Hyper-Threading Technology
  • Performance and Usage Models
    • Multithreading
    • Multitasking Environment
  • Programming Models and Multithreading
    • Parallel Programming Models
      • Domain Decomposition
    • Functional Decomposition
    • Specialized Programming Models
      • Producer-Consumer Threading Models
    • Tools for Creating Multithreaded Applications
  • Optimization Guidelines
    • Key Practices of Thread Synchronization
    • Key Practices of System Bus Optimization
    • Key Practices of Memory Optimization
    • Key Practices of Front-end Optimization
    • Key Practices of Execution Resource Optimization
    • Generality and Performance Impact
  • Thread Synchronization
    • Choice of Synchronization Primitives
    • Synchronization for Short Periods
    • Optimization with Spin-Locks
    • Synchronization for Longer Periods
      • Avoid Coding Pitfalls in Thread Synchronization
    • Prevent Sharing of Modified Data and False-Sharing
    • Placement of Shared Synchronization Variable
  • System Bus Optimization
    • Conserve Bus Bandwidth
    • Understand the Bus and Cache Interactions
    • Avoid Excessive Software Prefetches
    • Improve Effective Latency of Cache Misses
    • Use Full Write Transactions to Achieve Higher Data Rate
  • Memory Optimization
    • Cache Blocking Technique
    • Shared-Memory Optimization
      • Minimize Sharing of Data between Physical Processors
      • Batched Producer-Consumer Model
    • Eliminate 64-KByte Aliased Data Accesses
    • Preventing Excessive Evictions in First-Level Data Cache
      • Per-thread Stack Offset
      • Per-instance Stack Offset
  • Front-end Optimization
    • Avoid Excessive Loop Unrolling
    • Optimization for Code Size
  • Using Thread Affinities to Manage Shared Platform Resources
    • Using Shared Execution Resources in a Processor Core
• 8 64-bit Mode Coding Guidelines
  • Introduction
  • Coding Rules Affecting 64-bit Mode
    • Use Legacy 32-Bit Instructions When The Data Size Is 32 Bits
    • Use Extra Registers to Reduce Register Pressure
    • Use 64-Bit by 64-Bit Multiplies That Produce 128-Bit Results Only When Necessary
    • Sign Extension to Full 64-Bits
  • Alternate Coding Rules for 64-Bit Mode
    • Use 64-Bit Registers Instead of Two 32-Bit Registers for 64-Bit Arithmetic
    • Use 32-Bit Versions of CVTSI2SS and CVTSI2SD When Possible
    • Using Software Prefetch
• 9 Power Optimization for Mobile Usages
  • Overview
  • Mobile Usage Scenarios
  • ACPI C-States
    • Processor-Specific C4 and Deep C4 States
  • Guidelines for Extending Battery Life
    • Adjust Performance to Meet Quality of Features
    • Reducing Amount of Work
    • Platform-Level Optimizations
    • Handling Sleep State Transitions
    • Using Enhanced Intel SpeedStep® Technology
    • Enabling Intel® Enhanced Deeper Sleep
    • Multi-Core Considerations
      • Enhanced Intel SpeedStep® Technology
      • Thread Migration Considerations
      • Multi-core Considerations for C-States
• A Application Performance Tools
  • Intel® Compilers
    • Code Optimization Options
      • Targeting a Processor (-Gn)
      • Automatic Processor Dispatch Support (-Qx[extensions] and -Qax[extensions])
    • Vectorizer Switch Options
      • Loop Unrolling
      • Multithreading with OpenMP*
    • Inline Expansion of Library Functions (-Oi, -Oi-)
    • Floating-point Arithmetic Precision (-Op, -Op-, -Qprec, -Qprec_div, -Qpc, -Qlong_double)
    • Rounding Control Option (-Qrcd)
    • Interprocedural and Profile-Guided Optimizations
      • Interprocedural Optimization (IPO)
      • Profile-Guided Optimization (PGO)
  • Intel® VTune™ Performance Analyzer
    • Sampling
      • Time-based Sampling
      • Event-based Sampling
      • Workload Characterization
    • Call Graph
    • Counter Monitor
    • Intel® Tuning Assistant
  • Intel® Performance Libraries
    • Benefits Summary
    • Optimizations with the Intel® Performance Libraries
  • Enhanced Debugger (EDB)
  • Intel® Threading Tools
    • Intel® Thread Checker
    • Thread Profiler
  • Intel® Software College
• B Using Performance Monitoring Events
  • Pentium 4 Processor Performance Metrics
  • Pentium 4 Processor-Specific Terminology
    • Bogus, Non-bogus, Retire
    • Bus Ratio
    • Replay
    • Assist
    • Tagging
  • Counting Clocks
    • Non-Halted Clockticks
    • Non-Sleep Clockticks
    • Time Stamp Counter
  • Microarchitecture Notes
    • Trace Cache Events
    • Bus and Memory Metrics
      • Reads due to program loads
      • Reads due to program writes (RFOs)
      • Writebacks (dirty evictions)
    • Usage Notes for Specific Metrics
    • Usage Notes on Bus Activities
  • Metrics Descriptions and Categories
  • Performance Metrics and Tagging Mechanisms
    • Tags for replay_event
    • Tags for front_end_event
    • Tags for execution_event
  • Using Performance Metrics with Hyper-Threading Technology
  • Using Performance Events of Intel Core Solo and Intel Core Duo processors
    • Understanding the Results in a Performance Counter
    • Ratio Interpretation
    • Notes on Selected Events
• C IA-32 Instruction Latency and Throughput
  • Overview
  • Definitions
  • Latency and Throughput
    • Latency and Throughput with Register Operands
      • Table Footnotes
    • Latency and Throughput with Memory Operands
• D Stack Alignment
  • Stack Frames
    • Aligned esp-Based Stack Frames
    • Aligned ebp-Based Stack Frames
    • Stack Frame Optimizations
  • Inlined Assembly and ebx
• E Mathematics of Prefetch Scheduling Distance
  • Simplified Equation
  • Mathematical Model for PSD
    • No Preloading or Prefetch
    • Compute Bound (Case:Tc >= Tl + Tb)
    • Compute Bound (Case: Tl + Tb > Tc > Tb)
    • Memory Throughput Bound (Case: Tb >= Tc)
    • Example
• Index
• Intel Sales Offices