Intel ARCHITECTURE IA-32 - Manual (Page 467)

Using Performance Monitoring Events
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transactions of the writeback (WB) memory type for the FSB IOQ and
the BSQ can be an indication of how often this happens. It is less likely
to occur for applications with poor locality of writes to the 3rd-level
cache, and of course cannot happen when no 3rd-level cache is present.
Usage Notes for Specific Metrics
The difference between the metrics “Read from the processor” and
“Reads non-prefetch from the processor” is nominally the number of
hardware prefetches.
The paragraphs below cover several performance metrics that are based
on the Pentium 4 processor performance-monitoring event
“BSQ_cache_rerference”. The metrics are:
• 2nd-Level Cache Read Misses
• 2nd-Level Cache Read References
• 3rd-Level Cache Read Misses
• 3rd-Level Cache Read References
• 2nd-Level Cache Reads Hit Shared
• 2nd-Level Cache Reads Hit Modified
• 2nd-Level Cache Reads Hit Exclusive
• 3rd-Level Cache Reads Hit Shared
• 3rd-Level Cache Reads Hit Modified
• 3rd-Level Cache Reads Hit Exclusive
These metrics based on BSQ_cache_reference may be useful as an
indicator of the relative effectiveness of the 2nd-level cache, and the
3rd-level cache if present. But due to the current implementation of
BSQ_cache_reference in Pentium 4 and Intel Xeon processors, they
should not be used to calculate cache hit rates or cache miss rates. The
following three paragraphs describe some of the issues related to
BSQ_cache_reference, so that its results can be better interpreted.