Intel ARCHITECTURE IA-32 - Manual (Page 563)

Index
Index-3
floating-point stalls, 2-72
flow dependency, E-7
flush to zero, 5-22
FXCH instruction, 2-70
G
general optimization techniques, 2-1
branch prediction, 2-15
static prediction, 2-19
generating constants, 4-21
H
horizontal computations, 5-18
hotspots, 3-10
Hyper-Threading Technology, 7-1
avoid excessive software prefetches, 7-36
cache blocking technique, 7-38
conserve bus command bandwidth, 7-34
eliminate 64-K-aliased data accesses, 7-42
Front-end Optimization, 7-48
front-end optimization, 7-48
full write transactions, 7-37
functional decomposition, 7-8
improve effective latency of cache misses,
7-36
managing heavily-used execution
Resources, 7-59
memory optimization, 7-38
minimize data sharing between physical
processors, 7-39
Multitasking Environment, 7-4
optimization guidelines, 7-16
optimization with spin-locks, 7-25
parallel programming models, 7-7
per-instance stack offset, 7-46
per-thread stack offset, 7-44
placement of shared synchronization
variable, 7-31
prevent false-sharing of data, 7-30
preventing excessive evictions in first-level
data cache, 7-43
shared-memory optimization, 7-39
synchronization for longer periods, 7-26
synchronization for short periods, 7-22
system bus optimization, 7-33
thread synchronization, 7-19
tools for creating multithreaded
applications, 7-14
I
increasing bandwidth of memory fills, 4-39
increasing bandwidth of video fills, 4-39
indirect branch, 2-24
inline assembly, 4-5
inline expansion of library functions option,
A-6
inlined assembly blocks, D-10
inlined-asm, 3-15
insert word instruction, 4-14
instruction scheduling, 2-47, 4-40
instruction selection, 2-73
integer and floating-point multiply, 2-75, 2-76
integer divide, 2-76
integer-intensive application, 4-1
Intel Core Duo processor, 1-31
Intel Core Solo processor, 1-31
Intel Debugger, A-1
Intel Pentium D processor, 1-39
Intel Performance Library Suite, A-2
Intel Smart Cache, 1-31
interleaved pack with saturation, 4-8
interleaved pack without saturation, 4-10
interprocedural optimization, A-7
IPO. See interprocedural optimization