Intel ARCHITECTURE IA-32 - Manual (Page 561)

Index-1
Index
64-bit mode
default operand size, 8-1
introduction, 8-1
legacy instructions, 8-1
multiplication notes, 8-2
register usage, 8-2, 8-4
sign-extension, 8-3
software prefetch, 8-6
using CVTSI2SS & CVTSI2SD, 8-6
A
absolute difference of signed numbers, 4-24
absolute difference of unsigned numbers, 4-23
absolute value, 4-25
accesses per iteration, E-12, E-13
active power, 9-1
algorithm to avoid changing the rounding mode,
2-66
aligned ebp-based frame, D-4, D-6
aligned esp-based stack frames, D-4
Alignment
stack, 2-42
alignment, 2-29
code, 2-57
AoS format, 3-29
application performance tools, A-1
Arrays
Aligning, 2-39
automatic processor dispatch support, A-4
automatic vectorization, 3-18, 3-19
B
battery life, 9-1, 9-7
OS APIs, 9-8
performance options, 9-8
Branch Prediction, 2-15
branch prediction, 2-5
C
C4-state, 9-6
cache blocking techniques, 6-34
cache level, 6-6
cache management
simple memory copy, 6-46
smart cache, 1-31
video decoder, 6-45
video encoder, 6-45
calculating insertion for scheduling distance,
E-3
call graph profiling, A-13
changing the rounding mode, 2-65
checking for MMX technology support, 3-2
checking for Streaming SIMD Extensions
support, 3-3
classes (C/C++), 3-17
clipping to an arbitrary signed range, 4-26
clipping to an arbitrary unsigned range, 4-28
code optimization options, A-3
Code segment
Data in, 2-47