Intel ARCHITECTURE IA-32 - Manual (Page 59)

IA-32 Intel® Architecture Processor Family Overview
1-31
In-Order Retirement
The retirement unit in the Pentium M processor buffers completed µops
is the reorder buffer (ROB). The ROB updates the architectural state in
order. Up to three µops may be retired per cycle.
Microarchitecture of Intel ® Core™ Solo and
Intel ® Core™ Duo Processors
Intel Core Solo and Intel Core Duo processors incorporate an
microarchitecture that is similar to the Pentium M processor
microarchitecture, but provides additional enhancements for
performance and power efficiency. Enhancements include:
• Intel Smart Cache
This second level cache is shared between two cores in an Intel Core
Duo processor to minimize bus traffic between two cores accessing
a single-copy of cached data. It allows an Intel Core Solo processor
(or when one of the two cores in an Intel Core Duo processor is idle)
to access its full capacity.
• Stream SIMD Extensions 3
These extensions are supported in Intel Core Solo and Intel Core
Duo processors.
• Decoder improvement
Improvement in decoder and micro-op fusion allows the front end to
see most instructions as single
μ
op instructions. This increases the
throughput of the three decoders in the front end.
• Improved execution core
Throughput of SIMD instructions is improved and the out-of-order
engine is more robust in handling sequences of frequently-used
instructions. Enhanced internal buffering and prefetch mechanisms
also improve data bandwidth for execution.