Intel ARCHITECTURE IA-32 - Manual (Page 41)

IA-32 Intel® Architecture Processor Family Overview
1-13
correct execution, the results of IA-32 instructions must be committed
in original program order before they are retired. Exceptions may be
raised as instructions are retired. For this reason, exceptions cannot
occur speculatively.
When a µop completes and writes its result to the destination, it is
retired. Up to three µops may be retired per cycle. The reorder buffer
(ROB) is the unit in the processor which buffers completed µops,
updates the architectural state and manages the ordering of exceptions.
The retirement section also keeps track of branches and sends updated
branch target information to the branch target buffer (BTB). This
updates branch history. Figure 1-3 illustrates the paths that are most
frequently executing inside the Intel NetBurst microarchitecture: an
execution loop that interacts with multilevel cache hierarchy and the
system bus.
The following sections describe in more detail the operation of the front
end and the execution core. This information provides the background
for using the optimization techniques and instruction latency data
documented in this manual.
Front End Pipeline Detail
The following information about the front end operation is be useful for
tuning software with respect to prefetching, branch prediction, and
execution trace cache operations.
Prefetching
The Intel NetBurst microarchitecture supports three prefetching
mechanisms:
• a hardware instruction fetcher that automatically prefetches
instructions
• a hardware mechanism that automatically fetches data and
instructions into the unified second-level cache