Intel CONTROLLERS 413808 User Manual

Intel, Developer’s manual

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Order Number: 317805-001US

Intel

413808 and 413812 I/O

Controllers in TPER Mode

Developer’s Manual

October 2007

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Table of contents

Document Outline

Intel® 413808 and 413812 I/O Controllers in TPER Mode
1.0 Introduction
- Table 1. Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping
- Figure 1. TPER Architecture Overview
- 1.1 Design-in Considerations
  - 1.1.1 Software
- 1.2 Documentation References
  - Table 2. Documentation References
- 1.3 About This Document
  - 1.3.1 How To Read This Document
  - 1.3.2 Other Relevant Documents
- 1.4 About the Intel® 413808 and 413812 I/O Controllers in TPER Mode
  - Figure 2. Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram
- 1.5 Intel® 413808 and 413812 I/O Controllers in TPER Mode Features
- 1.6 Terminology and Conventions
2.0 Address Translation Unit (PCI-X)
- 2.1 Overview
  - Figure 3. ATU Block Diagram
  - Figure 4. ATU Queue Architecture Block Diagram
- 2.2 ATU Address Translation
- 2.3 Big Endian Byte Swapping
  - 2.3.1 Inbound Byte Swapping
    - Figure 9. Inbound Byte Swapping for 32-bit PCI
    - Figure 10. Inbound Byte Swapping for 64-bit PCI
  - 2.3.2 Outbound Byte Swapping
- 2.4 CompactPCI Hot-Swap
  - 2.4.1 Pin Interface
    - Table 7. Compact PCI Hot-Swap
    - 2.4.1.1 Compact PCI Hot-Swap Mode Select
      - Table 8. HS_FREQ Encoding
- 2.5 Expansion ROM Translation Unit
- 2.6 ATU Queue Architecture
- 2.7 ATU Error Conditions
- 2.8 Message-Signaled Interrupts
- 2.9 Internal Interrupts
- 2.10 Vital Product Data
  - 2.10.1 Configuring Vital Product Data Operation
  - 2.10.2 Accessing Vital Product Data
    - 2.10.2.1 Reading Vital Product Data
    - 2.10.2.2 Writing Vital Product Data
- 2.11 Multi-Function Support
  - 2.11.1 PCI-X Interface Control Parameters
    - Table 20. PCI-X Interface Control Parameters Usage
  - 2.11.2 PCI-X Interface Status Reporting
    - Table 21. PCI-X Host Interface Status Reporting Usage
- 2.12 Central Resource Functionality
- 2.13 Embedded Bridge Functionality
- 2.14 Register Definitions
3.0 Address Translation Unit (PCI Express)
- 3.1 Overview
  - Figure 22. ATU Block Diagram
  - Figure 23. ATU Queue Architecture Block Diagram
- 3.2 PCI Express Link Characteristics
- 3.3 ATU Address Translation
- 3.4 Big Endian Byte Swapping
  - 3.4.1 Inbound Byte Swapping
    - Figure 28. Inbound Byte Swapping
  - 3.4.2 Outbound Byte Swapping
- 3.5 Messaging Unit
- 3.6 PCI Express Messages
  - Table 125. Supported Message Types (Sheet 1 of 2)
- 3.7 Expansion ROM Translation Unit
- 3.8 ATU Queue Architecture
- 3.9 ATU Error Conditions
- 3.10 PCI Express Hot-Plug Support
- 3.11 Reset
- 3.12 Message-Signaled Interrupts
  - 3.12.1 Legacy Interrupts
  - 3.12.2 Internal Interrupts
- 3.13 Vital Product Data
  - 3.13.1 Configuring Vital Product Data Operation
  - 3.13.2 Accessing Vital Product Data
    - 3.13.2.1 Reading Vital Product Data
    - 3.13.2.2 Writing Vital Product Data
- 3.14 Multi-Function Support
  - 3.14.1 PCI Express Interface Control Parameters
    - Table 138. PCI Express Interface Control Parameters Usage (Sheet 1 of 2)
  - 3.14.2 PCI Express Interface Status Reporting
    - Table 139. PCI Express Interface Status Reporting Usage
- 3.15 Root Complex Functionality
- 3.16 Embedded Bridge Functionality
- 3.17 Register Definitions
4.0 Messaging Unit
- 4.1 Overview
- 4.2 Theory of Operation
- 4.3 Message Registers
  - 4.3.1 Outbound Messages
  - 4.3.2 Inbound Messages
- 4.4 Doorbell Registers
  - 4.4.1 Outbound Doorbells
  - 4.4.2 Inbound Doorbells
- 4.5 Messaging Unit Error Conditions
- 4.6 Message-Signaled Interrupts
- 4.7 Register Definitions
- 4.8 Power/Default Status
5.0 SRAM DMA Unit (SDMA)
- 5.1 Introduction
- 5.2 Overview
- 5.3 Theory of Operation
  - 5.3.1 Interrupt Control for SDMA
- 5.4 Register Definitions
6.0 SGPIO Unit
- 6.1 Overview
  - Figure 43. SGPIO Bus Overview
- 6.2 Theory of Operation
- 6.3 Clock Requirements
  - Figure 48. Clock Structure
- 6.4 Output Signals
- 6.5 SGPIO Unit Mode of Operations
- 6.6 Register Definitions
7.0 System Controller (SC) and Internal Bus Bridge
- 7.1 Overview
- 7.2 Theory of Operation
- 7.3 Internal Bus Bridge
- 7.4 System Controller Register Definitions
- 7.5 Internal Bus Bridge Register Definitions
8.0 SRAM Memory Controller
- 8.1 Overview
- 8.2 Glossary
  - Table 345. Commonly Used Terms
- 8.3 Theory of Operation
- 8.4 ECC Interrupts/Error Conditions
- 8.5 Parity Interrupts/Error Conditions
- 8.6 Register Definitions
9.0 Peripheral Bus Interface Unit
- Figure 62. The Peripheral Bus Interface Unit
- 9.1 Overview
- 9.2 Peripheral Bus Signals
- 9.3 Register Definitions
10.0 Interrupt Controller Unit
- 10.1 Overview
- 10.2 Theory of Operation
  - 10.2.1 Interrupt Controller Unit
- 10.3 The Intel XScale® Processor Exceptions Architecture
- 10.4 Intel® 413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface
  - 10.4.1 Interrupt Inputs
    - Table 377. Interrupt Input Pin Descriptions
  - 10.4.2 Outbound Interrupts
    - Table 378. Interrupt Output Pin Descriptions
- 10.5 The Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit
- 10.6 Default Status
  - Table 381. Default Interrupt Routing and Status Values
- 10.7 Interrupt Control Unit Registers
11.0 Timers
- Figure 71. Programmable Timer Functional Diagram
- Table 415. Timer Performance Ranges
- 11.1 Timer Operation
- 11.2 Timer Interrupts
- 11.3 Timer State Diagram
  - Figure 72. Timer Unit State Diagram
- 11.4 Timer Registers
- 11.5 Uncommon TCRX and TRRX Conditions
  - Table 427. Uncommon TMRx Control Bit Settings
12.0 SMBus Interface Unit
- 12.1 Overview
- 12.2 SMBus Interface
  - Table 428. SMBus Interface Pins
- 12.3 System Management Bus Interface
- 12.4 Register Definitions
13.0 UARTs
- 13.1 Overview
  - 13.1.1 Compatibility with 16550 and 16750
- 13.2 Signal Descriptions
  - Table 442. UART Signal Descriptions
- 13.3 Theory of Operation
- 13.4 Register Descriptions
14.0 I2C Bus Interface Units
- 14.1 Overview
- 14.2 Theory of Operation
- 14.3 I2C Bus Operation
- 14.4 Slave Mode Programming Examples
- 14.5 Master Programming Examples
- 14.6 Glitch Suppression Logic
- 14.7 Reset Conditions
- 14.8 Register Definitions
15.0 General Purpose I/O Unit
- 15.1 General Purpose Input Output Support
- 15.2 Register Definitions
16.0 PMON Unit
- 16.1 PMON Counters
- 16.2 Overview
  - Figure 106. Example Block Diagram of Component with Counter
  - 16.2.1 Clock Counter Control
    - Figure 107. Conceptual Diagram of Counter Array
- 16.3 Definitions
  - Figure 108. Example Block Diagram of Single PMON Counter
- 16.4 Data Collection
- 16.5 Non-Register-Based Interfaces
17.0 Clocking and Reset
- 17.1 Clocking Overview
- 17.2 Reset Overview
- 17.3 Reset Pins
  - Table 515. Reset Pin Summary
- 17.4 Device Function Select
  - Table 516. TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1)
  - Table 517. Non-TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=0)
- 17.5 Reset Strapping Options
  - Table 518. Reset Strap Signals (Sheet 1 of 2)
18.0 Test Logic Unit and Testability
- 18.1 Overview
- 18.2 IEEE 1149.1 Standard Test Access Port (TAP)
- 18.3 Definition of Terms
19.0 Peripheral Registers
- 19.1 Overview
- 19.2 Accessing Peripheral Memory-Mapped Registers
- 19.3 Accessing Peripheral Registers Using the Core Coprocessor Register Interface
- 19.4 Architecturally Reserved Memory Space
- 19.5 Default Memory Space Setup
  - Figure 124. Intel® 413808 and 413812 I/O Controllers in TPER Mode Memory Address Space
- 19.6 Peripheral Memory-Mapped Register Address Space
- 19.7 PCI Configuration Space
  - Table 547. Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility
- 19.8 Coprocessor Register Space
  - Table 548. Coprocessor Registers Assigned to Integrated Peripherals
  - Table 549. Coprocessor Register Locations (Sheet 1 of 4)

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