Intel CONTROLLERS 413808 - Manual (Page 225)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 225
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.87 Multi-Transaction Timer - MTT
This register controls the amount of time that the 4138xx arbiter allows a PCI initiator
to perform multiple back-to-back transactions on the PCI bus. The number of clocks
programmed in the MTT represents the insured time slice (measured in PCI clocks)
allotted to the current agent, after which the arbiter grants another agent that is
requesting the bus.
Table 114. Multi-Transaction Timer - MTT
Bit Default Description
07:03 00H
Timer Count Value (MTC): This field specifies the amount of time that grant remains asserted to a
master continuously asserting its request for multiple transfers. This field specifies the count in an
8-clock (PCI clock) granularity.
02:00 0H Reserved
PCI
IOP
Attributes
Attributes
7 4 0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+398H