Intel CONTROLLERS 413808 - Manual (Page 615)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 615
Interrupt Controller Unit—Intel
®
413808 and 413812
5 0
2
XINT13# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
4 0
2
XINT12# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
3 0
2
XINT11# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
2 0
2
XINT10# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
1 0
2
XINT9# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
0 0
2
XINT8# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
Table 404. FIQ Interrupt Source Register 1 — FINTSRC1 (Sheet 2 of 2)
Bit Default Description
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 7, Register 1