Intel CONTROLLERS 413808 - Manual (Page 46)

Intel
®
413808 and 413812—Introduction
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
46 Order Number: 317805-001US
1.5.6 Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the
4138xx. It uses interrupts to notify each system when new data arrives. The MU has
the following messaging mechanisms:
• Message Registers
• Doorbell Registers
Each allows a host processor or external PCI device and the 4138xx to communicate
through message passing and interrupt generation. The MU in conjunction with the ATU
in TPER mode.
1.5.7 DDR Memory Controller
DDR is not available on the 4138xx.
1.5.8 Peripheral Bus Interface
The Peripheral Bus Interface Unit is a data communication path to the Flash memory
components or other peripherals of 4138xx hardware system. Note, that Flash parts
must be compatible with the transport firmware. See the System/Software Architecture
Specfication and Design Guide Checklist for more information on supported Flash parts.
The PBI includes support for either 8/16 bit devices. To perform these tasks at high
bandwidth, the bus features a burst transfer capability which allows successive 8/16-bit
data transfers.
1.5.9 Performance Monitoring Unit
The Performance Monitoring Unit allows various events on the 4138xx to be monitored.
1.5.10 I
2
C Bus Interface Unit
There are three I
2
C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel
XScale
®
processor to serve as a master and slave device residing on the I
2
C bus. The
I
2
C unit uses a serial bus developed by Philips Semiconductor consisting of a two-pin
interface. The bus allows 4138xx to interface to other I
2
C peripherals and
microcontrollers for system management functions. It requires a minimum of hardware
for an economical system to relay status and reliability information on the I/O
subsystem to an external device. Also refer to I
2
C Peripherals for Microcontrollers
(Philips Semiconductor).
1.5.11 UART Unit
The 4138xx includes two UART units. The UART Unit allows the two Intel XScale
®
processors to serve as a master and slave device residing on the UART bus. The UART
unit uses a serial bus consisting of a two-pin interface. The bus allows 4138xx to
interface to other peripherals and microcontrollers. Also refer to 16550 Device spec
(National Semiconductor).
1.5.12 Interrupt Controller Unit
Each Intel XScale
®
processor supports an Interrupt Controller Unit. The Interrupt
Controller Unit (ICU) aggregates interrupt sources both external and internal of sources
of 4138xx to the Intel XScale
®
processor. The ICU supports high performance interrupt
processing with direct interrupt service routine vector generation on a per source basis.
Each source has programmability for masking, core processor interrupt input, and
priority.