Intel CONTROLLERS 413808 - Manual (Page 39)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 39
Introduction—Intel
®
413808 and 413812
1.1.1 Software
• PCI Configuration Space : For 4138xx in TPER mode (as with 81348), the PCI
configuration space presented is that of the Address Translation Unit (ATU) and it is
the responsibility of the Application Core firmware to setup things such as the
device ID per their design. When designing a system for In-place Upgrade, the
RAID ISV must determine if/how they will have host driver compatibility between
their stack running on 81348 with TPER firmware and their stack running on
IOP348 with standard firmware.
• RAID MetaData Format: The RAID ISV is responsible for meeting any
requirements with regards to Metadata format compatibility between their stack
running on 81348 with TPER firmware and their stack running on 81348 with
standard firmware.
• Host interface : Defined by the ISV, just as in 81348. When using TPER Silicon, MU
Circular queues and index registers are not available. SLI interface is only
relevant/available between the Application Core and Transport Core. With the same
interface as 81348, with the exception that the IOCB command and response rings
must be located in the Application Core SRAM space as opposed to DDR2 memory.
For full details on SLI interface requirements for TPER, please refer to the SCDL
Architecture Specification listed in Table 2, “Documentation References” on
page 40 .
• SDMA (SRAM DMA) Engine: Since there is no ADMA without DDR2, a separate
DMA engine, the SRAM DMA, is provided to allow for the Application Core the ability
to DMA command/status as part of its host messaging interface. The engine is
different from ADMA, no chaining or special features. All access is direct register
(no coprocessor access) as opposed to DDR2 memory descriptor based processing
for ADMA. The SDMA chapter is found in this manual.
• SRAM ECC: The SRAM is a shared resource between the Application Core and the
Transport Core in TPER. The Ttransport Core handles the initial enabling of ECC and
scrubbing of SRAM for the entire region before the common boot code allows
transfers execution to the Application Core. However, the Transport Core ignores
ECC errors in the Application Core SRAM region and expects that the Application
Core handles and clears ECC interrupts per specification. Similarly, the Transport
Core handles all ECC interrupts for the Transport Core region of SRAM and asserts
(hanger/dump) in the event that a multi-bit error occurs in its region. The SRAM
chapter is found in this manual.
—
Important Notes:
-
The Application Core must ignore all ECC interrupts until after it has successfully
completed CONFIG_SLI_PORT since up until that time, theTransport Firmware monitors
ECC errors for the entire SRAM region.
-
In the event that the Application Ccore uses a PRG other than the TPER firmware
(diagnostic overlay for internal test purposes when available), the Application Ccore must
ignore the ECC interrupt for the entire SRAM region.