Intel CONTROLLERS 413808 - Manual (Page 331)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 331
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
03 0
Received Master Abort Interrupt - Set when an Unsupported Request (UR) completion is received by any
function.
Generates the ATU Error Interrupt
02 0
Signaled Target Abort Interrupt - Set when a request is completed using a Completer Abort (CA)
Completion Status by any function.
Generates the ATU Error Interrupt
01 0
Received Target Abort Interrupt - Set when a completion with Completer Abort Completion Status is
received by any function.
Generates the ATU Error Interrupt
00 0
Master Data Parity Error Interrupt - Set when the Parity Error Response is enabled and any function
transmits a Poisoned Write TLP or receives a Poisoned Completion TLP.
Generates the ATU Error Interrupt
Table 182. ATU Interrupt Status Register - ATUISR (Sheet 3 of 3)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rz
rz
rz
rz
rz
rz
rc
rc
ro
ro
rc
rc
rc
rc
ro
ro
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
rc
rc
rc
rc
rz
rz
rz
rz
rc
rc
rc
rc
ro
ro
ro
ro
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+078H