Intel CONTROLLERS 413808 - Manual (Page 120)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
120 Order Number: 317805-001US
Inbound
Configuration
Write
Completion
Message
Uncorrectable
Data Error
(PCI-X)
None.
Inbound Read
Request
Uncorrectable
Data Error (All)
None.
Inbound Write
Request
Uncorrectable
Data Error (All)
Signal PERR# .
(All) Detected Parity Error - bit 15 Detected Parity Error - bit 9 ATUIMR bit 7
(PCI-X2) ECCLOG Updated N/A N/A
Outbound Read
Completion
Uncorrectable
Data Error (All)
Signal PERR# and SERR# .
(PCI-X Master Parity Error - bit 8 Master Parity Error - bit 0 ATUIMR bit 2
(PCI-X) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(PCI-X) N/A SERR# Detected - bit 4 ATUCR bit 9
(PCI-X) Detected Parity Error - bit 15 Detected Parity Error - bit 9 ATUIMR bit 7
(PCI-X2) ECCLOG Updated N/A N/A
Outbound Split
Write
Uncorrectable
Data Error
Message (PCI-X)
Signal SERR# .
(PCI-X) Master Parity Error - bit 8 Master Parity Error - bit 0 ATUIMR bit 2
(PCI-X) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(PCI-X) N/A SERR# Detected - bit 4 ATUCR bit 9
(PCI-X)
Received Split Completion Error
Message - bit 29
Received Split Completion Error
Message - bit 12
ATUIMR bit 9
Inbound
Configuration
Write Request
Uncorrectable
Data Error (All)
Signal PERR# . Initiate an Uncorrectable Split Write Data Error Message addressed to the
Requester (PCI-X Mode Only).
(PCI-X) N/A
Initiated Split Completion Error
Message - bit 13
ATUIMR bit 10
(All) Detected Parity Error - bit 15 Detected Parity Error - bit 9 ATUIMR bit 7
(PCI-X2) ECCLOG Updated N/A N/A
Split Completion
Message
Uncorrectable
Data Error
(PCI-X)
Signal PERR# and SERR# .
Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 2 of 5)
Error Condition
(Bus Mode
a
)
Bits Set in
ATU Status Register
(ATUSR
b
)
or
PCI-X Status Register
(PCIXSR
c
)
and/or
ECC Logging Registers
d
(ECCLOG)
Bits Set in
ATU Interrupt Status
Register (ATUISR)
Interrupt Mask Bit in
ATUIMR or ATUCR
PCI Bus Error Response (i.e., signal Target-Abort, signal Master-Abort etc.)