Table 130. atu outbound data flow ordering rules, 130 atu outbound data flow ordering rules, Table 130, “atu outbound data flow – Intel CONTROLLERS 413808 User Manual
Page 265: Example 2. inbound queue completion
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
265
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
Definitions of the terms used in
and
are as follows. PCI terms are
noted in parenthesis:
These transaction ordering rules define the way in which data moves in both directions
through the ATU. In
and
NO
response in a box means that based
on ordering rules, the current transaction (the row) can not pass the previous
transaction (the column) under any circumstance. A
Yes
response in the box means
that the current transaction is allowed to pass the previous transaction but is not
required to, based on whether a consistent view of data or prevention of deadlocks are
needed.
In the case of inbound write operations, multiple transactions may exist within the
IPHQ and the corresponding IPDQ at any point in time. The ordering of these
transactions is based on a time stamp basis. Transactions entering the queue are
stamped with a relative time in relation to all other transactions moving in a similar
direction.
Table 130. ATU Outbound Data Flow Ordering Rules
Row Pass Column?
Outbound
Write or
Message
Request
Outbound
Read
Request
Outbound
Configuratio
n Write
Request
Outbound
Read
Completion
Outbound
Configuratio
n or I/O
Write
Completion
Outbound Write or
Message Request
No
Yes
Yes
Yes
Yes
Outbound Read Request
No
No
No
Yes
Yes
Outbound Configuration
Write Request
No
No
No
Yes
Yes
Outbound Read
Completion
No
Yes
Yes
Yes
Yes
Outbound Configuration
or I/O Write Completion
No
Yes
Yes
Yes
Yes
Example 2. Inbound Queue Completion
A6499-01
Outbound Read Queue
B
B
B
B
B
B
B
B
Inbound Write Queue
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
Outbound Read Queue
B
B
B
B
B
B
B
B
Inbound Write Queue
C
C
C
C
C
C
C
C
PCI Bus
Internal Bus