Intel CONTROLLERS 413808 - Manual (Page 696)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
696 Order Number: 317805-001US
14.2.3.1 START Condition
The START condition (bits 1:0 of the ICR set to 01
2
) initiates a master transaction or
repeated START. Software must load the target slave address and the R/W# bit in the
IDBR (see Section 14.8.4, “I2C Data Buffer Register x — IDBRx” on page 720 ) before
setting the START ICR bit. The START and the IDBR contents are transmitted on the I
2
C
bus when the ICR Transfer Byte bit is set. The I
2
C bus stays in master-transmit mode
when a write is requested or enters master-receive mode when a read is requested. For
a repeated start (a change in read or write or a change in the target slave address), the
IDBR contains the updated target slave address and the R/W# bit. A repeated start
enables multiple transfers to different slaves without giving up the bus.
The START condition is not cleared by the I
2
C unit. When arbitration is lost while
initiating a START, the I
2
C unit may re-attempt the START when the bus becomes free.
See Section 14.3.3, “Arbitration” on page 700 for details on how the I
2
C unit functions
under those circumstances.
14.2.3.2 No START or STOP Condition
No START or STOP condition (bits 1:0 of the ICR set to 00
2
) is used in master-transmit
mode while the 4138xx is transmitting multiple data bytes (see Figure 93 ). Software
writes the data byte, sets the IDBR Transmit Empty bit in the ISR (and interrupt when
enabled), and clears the Transfer Byte bit in the ICR. The software then writes a new
byte to the IDBR and sets the Transfer Byte ICR bit, which initiates the new byte
transmission. This continues until the software sets the START or STOP bit. The START
and STOP bits in the ICR are not automatically cleared by the I
2
C unit after the
transmission of a START, STOP or repeated START.
After each byte transfer (including the Ack/Nack bit) the I
2
C unit holds the SCL line low
(inserting wait states) until the Transfer Byte bit in the ICR is set. This action notifies
the I
2
C unit to release the SCL line and allow the next information transfer to proceed.
14.2.3.3 STOP Condition
The STOP condition (bits 1:0 of the ICR set to 10
2
) terminates a data transfer. In
master-transmit mode, the STOP bit and the Transfer Byte bit in the ICR must be set to
initiate the last byte transfer (see Figure 93 ). In master-receive mode, to initiate the
last transfer the 4138xx must set the Ack/Nack bit, the STOP bit, and the Transfer Byte
bit in the ICR. Software must clear the STOP condition after it is transmitted.
Figure 94. START and STOP Conditions
Data byte
Ack/
Nack
R/W# START Target Slave Address
R/W# Data Byte STOP
No START or STOP Condition
START Condition
STOP Condition
Ack/
Nack
Ack/
Nack
B6284-01