Intel CONTROLLERS 413808 - Manual (Page 222)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
222 Order Number: 317805-001US
2.14.84 PCI Interface Error Upper Address Register - PCIEUAR
When PCIECSR bit 0 is set and the PCI error detected included a DAC cycle, this
register represents the upper 32-bit address of where the error was detected on the
PCI bus. This register is used in conjunction with the Section 2.14.83, “PCI Interface
Error Address Register - PCIEAR” on page 221 . One error can be detected and logged.
The software knows which PCI address had the error by reading this register and
decoding contents of the PCIECSR. For error details, see Section 2.7, “ATU Error
Conditions” on page 94 ).
Note: The “PCI Interface Error Control and Status Register - PIECSR” , “PCI Interface Error
Address Register - PCIEAR” , and “PCI Interface Error Upper Address Register -
PCIEUAR” report the original transaction when an error is detected on the current
transaction. For example, when the Split Completion of an original Outbound Read
request had an error, the information regarding the Outbound Read is reported.
Table 111. PCI Interface Error Upper Address Register - PCIEUAR
Bit Default Description
31:00 0000 000H
Upper 32-bit Address - When bit 0 of the PCIECSR is set, this register represents the upper 32 bits of
the PCI Address.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+388H