Intel CONTROLLERS 413808 - Manual (Page 698)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
698 Order Number: 317805-001US
14.3.1.1 Addressing a Slave Device
As a master device, the I
2
C unit must compose and send the first byte of a transaction.
This byte consists of the slave address for the intended device and a R/W# bit for
transaction definition. The slave address and the R/W# bit are written to the IDBR (see
Figure 95 ).
The first byte transmission must be followed by an Ack pulse from the addressed slave.
When the transaction is a write, the I
2
C unit remains in master-transmit mode and the
addressed slave device stays in slave-receive mode. When the transaction is a read,
the I
2
C unit transitions to master-receive mode immediately following the Ack and the
addressed slave device transitions to slave-transmit mode. When a Nack is returned,
the I
2
C unit aborts the transaction by automatically sending a STOP and setting the ISR
bus error bit.
When the I
2
C unit is enabled and idle (no bus activity), it stays in slave-receive mode
and monitors the I
2
C bus for a START signal. Upon detecting a START pulse, the I
2
C
unit reads the first seven bits and compares them to those in the I
2
C Slave Address
Register (ISAR) and the general call address (00H). When the bits match those of the
ISAR register, the I
2
C unit reads the eighth bit (R/W# bit) and transmits an Ack pulse.
The I
2
C unit either remains in slave-receive mode (R/W# = 0) or transitions to
slave-transmit mode (R/W# = 1). See Section 14.3.6, “General Call Address” on
page 707 for actions when a general call address is detected.
Figure 95. Data Format of First Byte in Master Transaction
4 0
7-Bit I2C Slave Address
7
Read/Write Transaction
MSB LSB
(0) Write
(1) Read
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