Intel CONTROLLERS 413808 - Manual (Page 518)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
518 Order Number: 317805-001US
8.3.2.3 SRAM Write Sequence
Write transactions require ECC codes to be generated and stored in the SRAM array
with the data being written. The behavior is different depending on the size of the data
being written. Section 8.3.3, “Error Correction and Detection” on page 519 explains the
ECC algorithm in more detail.
1. Each of the SMCU inbound memory transaction ports decodes the address to
determine if the transaction should be claimed.
— If the address falls in the SRAM address range indicated by the SRAMBAR and
SRAMUBAR the SMCU claims the transaction.
2. Once the SMARB selects the highest priority port transaction, it forwards the
transaction to the SRAM control block.
— The ECC logic generates the ECC code for the data to be written.
— The SRAM Control Block drives the new data to the memory array each cycle
until the transaction is completed with the byte count expiring.
— For each burst issued, the SRAM Control Block increments the address by
sixteen.
— When the data to write is less than an aligned DWORD, the SRAM Control Block
will perform a read-modify-write of the entire 4 byte aligned DWORD and
incorporate the new data while regenerating ECC.