Intel CONTROLLERS 413808 - Manual (Page 261)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 261
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.8 ATU Queue Architecture
ATU operation and performance depends on queueing mechanism implemented
between internal bus interface and PCI Express interface. Figure 23 indicates the ATU
queue architecture consists of separate inbound and outbound queues. The function of
each queue is described in the following sections.
3.8.1 Inbound Queues
The inbound data queues of the ATU support transactions initiated on a PCI Express
Link and targeted at either 4138xx local memory or a 4138xx memory mapped
register. Table 126 details the name and sizes of the ATU inbound data queues.
3.8.1.1 Inbound Posted Queue Structure
The ATU Inbound Posted Queues consist of the inbound posted data queue (IPDQ) and
the inbound posted header queue (IPHQ). The inbound posted data queue holds the
data for posted (memory/message) transactions moving from a PCI Express Link to the
internal bus and the header queue holds the corresponding address. The inbound
posted data queue has a queue depth of 4 KBytes and moves posted transactions from
the PCI Express Link to the internal bus. The corresponding header queue, IPHQ, is
capable of holding 8 entries.
The following rules apply to the PCI Express Link interface and govern the acceptance
of data into inbound posted queues:
• Posted transactions are drained from the head of the queue when the master
interface has acquired bus ownership and transaction ordering and priority have
been satisfied (see Section 3.8.3 ). A memory write transaction is considered
drained from the queue when the entire amount of data entered on the PCI Express
Link has been accepted by the internal bus target. Error conditions resulting in the
cancellation of a write transaction only flush the transaction at the head of the data
and address queue. All other transactions within the queues are considered still
valid.
Table 126. Inbound Queues
Queue Mnemonic Queue Name
Queue Size
(Bytes)
IPDQ Inbound Posted Data Queue 3.75 KBytes (240 credits)
IPHQ Inbound Posted Header Queue 16 Headers
INPQ Inbound Non Posted Queue 8 Headers a
a. Non Posted request with data (I/O and Configuration Writes) always use the 3DW header. The
associated data is always 1 DW in size and can be stored the 4th DW of the header queue.
ICPLDQ Inbound Completion Data Queue 4 KBytes (infinite credits) b
b. As a PCI Express endpoint the ATU must pre-allocate buffer space before issuing a read request. The
ATU is required to advertise infinite credits.
ICPLHQ Inbound Completion Header Queue 4 Headers (infinite)