Intel CONTROLLERS 413808 - Manual (Page 83)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 83
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.6 ATU Queue Architecture
ATU operation and performance depends on the queueing mechanism implemented
between the internal bus interface and PCI bus interface. As indicated in Figure 4 , the
ATU queue architecture consists of separate inbound and outbound queues. The
function of each queue is described in the following sections.
2.6.1 Inbound Queues
The inbound data queues of the ATU support transactions initiated on a PCI bus and
targeted at either 4138xx local memory or a 4138xx memory mapped register. Table 9
details the name and sizes of the ATU inbound data queues.
2.6.1.1 Inbound Write Queue Structure
The ATU Inbound Write Queues consist of the inbound write data queue and the
inbound write address queue. The inbound write data queue holds the data for memory
write transactions moving from a PCI Bus to the internal bus and the address queue
holds the corresponding address of the transactions in the data queues. The inbound
write queue, IWQ, has a queue depth of 4 KBytes and moves write transactions from
the PCI bus to the internal bus. The corresponding address queue, IWADQ, is capable
of holding 4 address entries. The queue pair is capable of holding up to 4 memory write
(or MWI when operating in the conventional PCI mode) transactions.
The following rules apply to the PCI bus interface and govern the acceptance of data
into IWQ and address into the tail of the IWADQ:
• A memory write operation claimed by the target PCI interface on the PCI bus is
accepted into the address and data queues when the IWADQ has at least one
address entry available.
• When operating in the conventional PCI mode, when the IWQ reaches a full state
while filling, a disconnect with data is signaled to the master of the transaction.
• When operating in the PCI-X mode, when the IWQ reaches a full state while filling,
a disconnect at next ADB is signaled to the master of that transaction.
Memory write transactions are drained from the head of the queue when the master
interface has acquired bus ownership and transaction ordering and priority have been
satisfied (see Section 2.6.3 ). A memory write transaction is considered drained from
the queue when the entire amount of data entered on the PCI bus has been accepted
by the internal bus target. Error conditions resulting in the cancellation of a write
transaction only flush the transaction at the head of the data and address queue. All
other transactions within the queues are considered still valid.
Table 9. Inbound Queues
Queue Mnemonic Queue Name
Queue Size
(Bytes)
IWQ Inbound Write Data Queue 4 KBytes (4*1KB)
IWADQ Inbound Write Address Queue 4 Transaction Addresses
IRQ Inbound Read Data Queue 4 KBytes (4*1KB)
IDWQ
Inbound Delayed Write address/data
Queue
1 Transaction
ITQ Inbound Transaction Queue 8 Addresses/Commands