Intel CONTROLLERS 413808 - Manual (Page 73)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 73
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
The PCI interface is responsible for completing the outbound write transaction with the
PCI address translated from the OWADQ and the data in the OWQ. The data flow for an
outbound write transaction on the PCI bus is summarized in the following statements:
• ATU PCI interface requests PCI bus, when completed internal bus transaction is in
OWADQ and data associated with transfer in OWQ. Once bus is granted, PCI master
interface writes PCI translated address from OWADQ to PCI bus and waits for
transaction to be claimed.
• When Master Abort seen during address phase, transaction flushed and
OWADQ/OWQ are cleared. Section 2.7.5 has full details on PCI master abort
conditions during outbound transactions.
• In conventional PCI mode, once PCI write transaction is claimed, the PCI interface
transfers data from the OWQ to the PCI bus until one of the following is true:
— PCI target signals a Retry or Disconnect. The ATU PCI master attempts to
reacquire the PCI bus to complete the write transaction.
— GNT# signal is deasserted and master latency timer has expired. In this case,
master interface attempts to reacquire PCI bus and complete write transaction.
— PCI target signals a Target-Abort. In this case, OWQ and OTQ are cleared and
transaction aborted. Appropriate error bits are set as defined in Section 2.7.6 .
— Transaction terminates normally by transferring all data (full byte count)
associated with it. The write address is removed from the OWADQ and the
interface returns to idle.
• In PCI-X mode, once the PCI memory write transaction is claimed, the PCI interface
transfers data from the OWQ to the PCI bus until one of the following is true:
— The PCI target signals a Retry or Single Data Phase Disconnect. The ATU PCI
initiator attempts to reacquire the PCI bus to complete the write transaction.
— Reacquire the PCI bus to complete the write transaction.
— GNT# signal is deasserted and the master latency timer has expired. In this
case, the master interface attempts to reacquire the PCI bus and complete the
write transaction.
— PCI target signals a Target-Abort. In this case, the OWQ and OWADQ are
cleared and the transaction is aborted. The appropriate error bits are set as
defined in Section 2.7.6 .
— Transaction terminates normally with Satisfaction of Byte Count. The write
address is removed from the OWADQ and the interface returns to idle.
• In the PCI-X mode, once the PCI I/O write transaction is claimed, the PCI interface
transfers data from the OWQ to the PCI bus until one of the following is true:
— PCI target signals a Retry. The ATU PCI initiator attempts to reacquire the PCI
bus to complete the write transaction.
— Transaction terminates normally with Satisfaction of Byte Count or with Single
Data Phase Disconnect. The write address is removed from the OWADQ and the
interface returns to idle.
— PCI target signals a Target-Abort. In this case, the OWQ and OWADQ are
cleared and the transaction is aborted. The appropriate error bits are set as
defined in Section 2.7.6 .
— Transaction terminates with Split Response Termination. The write address is
removed from the OWADQ and the interface returns to idle only when it
receives the corresponding Split Completion Message.
When an uncorrectable data error is encountered ( PERR# detected), the master
interface continues writing data to clear the queue.
In the conventional PCI mode when the PCI target deasserts TRDY# , no action is
taken by the ATU master other than inserting wait states.