Intel ARCHITECTURE IA-32 - Manual (Page 402)

IA-32 Intel® Architecture Optimization
7-56
PackageID[ProcessorNUM] = PACKAGE_ID;
CoreID[ProcessorNum] = CORE_ID;
SmtID[ProcessorNum] = SMT_ID;
CacheID[ProcessorNUM] = CACHE_ID;
// Only the target cache is stored in this example
ProcessorNum++;
}
ThreadAffinityMask <<= 1;
}
NumStartedLPs = ProcessorNum;
CacheIDBucket is an array of unique Cache_ID values. Allocate an array
of NumStartedLPs count of entries in this array for the target cache level.
CacheProcessorMask is a corresponding array of the bit mask of logical
processors sharing the same target level cache, these are logical
processors with the same Cache_ID.
The algorithm below assumes there is symmetry across the modular
boundary of target cache topology if more than one socket is populated
in an MP system, and only the topology of the target cache level is discovered.
Topology of other cache level can be determined in a similar manner.
// Bucket Cache IDs and compute processor mask for the target cache of every package.
CacheNum = 1;
CacheIDBucket[0] = CacheID[0];
ProcessorMask = 1;
CacheProcessorMask[0] = ProcessorMask;
Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors
Sharing the Same Cache (Contd.)