Document Outline

• Introduction 1-1
• Functional Description 2-1
• Configuration 3-1
• Programming 4-1
• Unpacking and Special Handling Instructions
• Revision History
• PEP Modular Computers Two Year Limited Warranty
• Preface
• 1.1 Product Overview
• 1.2 IndustryPack Flexibility
• 1.3 Controller eXtension Connector
• 1.4 Front Panel and I/O Configuration
  • Figure 1.1 Front Panel Options
• 1.5 Features
  • Figure 1.2 MC68EN360 Channel Assignment
• 1.6 Specifications
• 1.7 Ordering Information
• 1.8 Related Publications
• 1.9 Schematic Board Layout
  • Introduction
• 2.1 VM162/VM172 Block Diagram
• 2.2 CPU Options
  • Table 2.1: CPU Options
  • 2.3 Memory
    • 2.3.1 DRAM/FLASH
      • Table 2.2: DRAM/FLASH Options
    • 2.3.2 SRAM
    • 2.3.3 Boot ROM (optional)
    • 2.3.4 EEPROM
  • 2.4 Communication Controller 68EN360 (QUICC)
    • 2.4.1 Use of 68EN360 Communication Ports
    • 2.4.2 Use of 68EN360 Memory Controller
      • Table 2.3: 68EN360 CS Line Connection
    • 2.4.3 Use of 68EN360 Interrupt Controller
      • Table 2.4: External Signal Connection
    • 2.4.4 Use of 68EN360 DMA Channels
  • 2.5 VMEbus Interface
    • 2.5.1 VME Master Interface
      • 2.5.1.1 Supported Data Transfer Types (VMEbus AM C...
        • Table 2.5: External Signal Connection
      • 2.5.1.2 VME Address Map
        • Table 2.6: Generated AM Codes
    • 2.5.2 System Controller Functions
      • 2.5.2.1 Automatic First-Slot Detection
      • 2.5.2.2 SYSCLK* Generator
      • 2.5.2.3 SYSRES* Generator
      • 2.5.2.4 VMEbus Monitor
    • 2.5.3 VME Slave Interface
      • 2.5.3.1 Dual-Ported RAM
      • 2.5.3.2 Mailbox Interrupt
    • 2.5.4 VME Address Map from the VME Side
      • Table 2.7: VME Address Map
    • 2.5.5 VME Control/Status Register
• 2.6 Board Control Logic
  • 2.6.1 Boot Decoder Logic
  • 2.6.2 Interrupt Control
    • 2.6.2.1 Internal Requests
    • 2.6.2.2 External Autovectored Interrupt Requests
      • Table 2.8: External Autovectored Interrupts
    • 2.6.2.3 VME Interrupt Mask Register
  • 2.6.3 Bus Timer
  • 2.6.4 Watchdog Timer
  • 2.6.5 Board Control/Status Register
• 2.7 Special Functions
  • 2.7.1 Real Time Clock
  • 2.7.2 Serial EEPROM
  • 2.7.3 TICK Timer
  • 2.7.4 General Purpose Timer
  • 2.7.5 DMA Transfers
  • 2.7.6 Data Retention for RTC and SRAM
  • 2.7.7 Front Panel Buttons and LED Ports
    • Figure 2.1 LED Port and Button Location
    • 2.7.7.1 RESET/ABORT Button
    • 2.7.7.2 LED Port
• 2.8 Serial Communication Ports
  • Figure 2.2 MC68EN360 Channel Assignment
    • Table 2.9: Serial Communication Port Configuration...
  • 2.8.1 Ethernet/SER4 Port
  • 2.8.2 SER1, SER2 and SER3 Ports
  • 2.8.3 TERM Pinout
• 2.9 CXC Interface
  • Table 2.10: CXC Pinouts using the 68(EN)360
    • 1) On a standard VM162/VM172 board, these signals ...
    • 2) On a standard VM162/VM172 board, these signals ...
    • 3) On PA13, a 24 MHz clock signal is routed via ju...
    • 4) These signals are routed both to the base board...
  • Table 2.11: Further Explanation of 68(EN)360 Mnemo...
• 2.10 IndustryPack (IP) Interface
  • 2.10.1 Overview
  • 2.10.2 Features
  • 2.10.3 Optional IP features, not supported
  • 2.10.4 IP Interface Controller
  • 2.10.5 IP Reset Control
  • 2.10.6 IP Clock Control
  • 2.10.7 IP Interrupt Control
  • 2.10.8 IP Memory Size Control
  • 2.10.9 IP Interface Address Map
  • 2.10.10 IP Interrupt Control Register
  • 2.10.11 IP Slot Control Register
  • 2.10.12 IP Connectors
    • 2.10.12.1 IP I/O Connector, Pinout
    • 2.10.12.2 IP I/O Flat Cable Connector, Pinout
    • 2.10.12.3 IP I/O DSUB Frontpanel Connector, Pinout...
      • Functional Description
• 3.1 Default Jumper Settings
  • 3.1.1 Jumper Default Settings (Component Side)
  • 3.1.2 Jumper Default Settings (Solder Side)
• 3.2 Jumper Description (Component Side)
  • Figure 3.1 VM162/VM172 Jumper Layout (Component Si...
  • 3.2.1 VME Boot
  • 3.2.2 ROM Boot
  • 3.2.3 Protective Ground - Signal Ground
  • 3.2.4 VME SYSRES*
  • 3.2.5 CXC Mode
• 3.3 Jumper Description (Solder Side)
  • Figure 3.2 VM162/VM172 Jumper Layout (Solder Side)...
  • 3.3.1 CPU Type
  • 3.3.2 CPU Power Supply
  • 3.3.3 CPU (Bus) Clock
  • 3.3.4 SRAM Size
  • 3.3.5 Communications Clock
  • 3.3.6 EEPROM Write Protection
  • 3.3.7 JTAG Chain
  • 3.3.8 SRAM Data Retention
  • 3.3.9 BERR1 Timeout
  • 3.3.10 Backup Current Test Bridge
    • Configuration
• 4.1 VM162/VM172 Address Map
• 4.2 Initializing the 68EN360
  • 4.3 Initializing the Cache
    • Programming
      • APPENDIX MEMORY PIGGYBACKS
      • Ordering Information
• 1 DM600
  • 1.1 Jumper Location
• 2 DM601
  • 2.1 Jumper Location
• 3 DM602
  • 3.1 Jumper Location
• 4 DM603
  • 4.1 Jumper Location
• 5 DM604
  • 5.1 Jumper Location
    • APPENDIX SI6 PIGGYBACKS
    • Ordering Information
• 1 SI6-10B2
  • 1.1 Specifications
  • 1.2 Connector
• 2 SI6-10B5
  • 2.1 Specifications
  • 2.2 Connector
• 3 SI6-10BT
  • 3.1 Specifications
  • 3.2 Connector
  • 3.3 Jumper Location
• 4 SI6-PB485-ISO
  • 4.1 Specifications
  • 4.2 Connector
  • 4.3 Jumper Location
    • APPENDIX
• 1 Introduction
• 2 System Operation
  • 2.1 Startup
  • 2.2 Entering the Command Mode
• 3 Programming FLASH Memory
  • 3.1 Preparing the Image
  • 3.2 Programming with Motorola S-Records
  • 3.3 Programming from an Absolute Address
  • 3.4 Boot Wait Time
• 4 Command Reference
  • 4.1 Boot Wait
  • 4.2 Load Flash
  • 4.3 Memory Display
  • 4.4 Port Format
  • 4.5 Reset System
  • 4.6 Help
    • APPENDIX CXC. CONTROLLER EXTENSION CONNECTOR
• 1 CXC Address Range
• 2 CXC Generic Pinouts
• 3 CPU Pinout Cross Reference
  • Table 3.0.1: Comparsion of 68302 / 68(EN)360 Funct...
• 4 Timing
• 5 Controller Extension Connectors
  • APPENDIX OS-9 CABLING
• 1 OS-9 System <-> Terminal
  • 1.1 Software (XON/XOFF) or no Handshake
    • 1.1.1 15-pin Connector on OS-9 Side
    • 1.1.2 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
    • 1.1.3 6-pin RJ12 Connector on OS-9 Side
  • 1.2 Hardware Handshake (Set Terminal to CTS/DTR Ha...
    • 1.2.1 15-pin Connector on OS-9 Side
    • 1.2.2 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
• 2 OS-9 System <-> PC
  • 2.1 Software (XON/XOFF) or no Handshake
    • 2.1.1 15-pin Connector on OS-9 Side, 25-pin Connec...
    • 2.1.2 15-pin Connector on OS-9 Side, 9-pin Connect...
    • 2.1.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
    • 2.1.4 6-pin RJ12 Connector on OS-9 Side, 25-pin Co...
    • 2.1.5 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
    • 2.1.6 6-pin RJ12 Connector on OS-9 Side, 9-pin Con...
  • 2.2 Hardware Handshake (Select RTS/CTS Handshake o...
    • 2.2.1 15-pin Connector on OS-9 Side, 25-pin Connec...
    • 2.2.2 15-pin Connector on OS-9 Side, 9-pin Connect...
    • 2.2.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
    • 2.2.4 8-pin RJ45 Connector on OS-9 Side (SMART I/O...
• 3 OS-9 System <-> Modem
  • 3.1 15-pin Connector
  • 3.2 8-pin RJ45 Connector (SMART I/O)
• 4 OS-9 System <-> OS-9 System
  • 4.1 Software (XON/XOFF) or no Handshake
    • 4.1.1 15-pin Connector
    • 4.1.2 8-pin RJ45 Connector (SMART I/O)
    • 4.1.3 6-pin RJ12 Connector
  • 4.2 Hardware Handshake
    • 4.2.1 15-pin Connector
    • 4.2.2 8-pin RJ45 Connector (SMART I/O)