Document Outline

• Features
• 1. Pin Configurations
  • 1.1 Pin Descriptions
    • 1.1.1 VCC
    • 1.1.2 GND
    • 1.1.3 Port A (PA7:PA0)
    • 1.1.4 RESET
    • 1.1.5 Port B (PB7:PB0)
    • 1.1.6 LSW
    • 1.1.7 VBAT
• 2. Overview
• 3. About
  • 3.1 Resources
  • 3.2 Code Examples
  • 3.3 Data Retention
  • 3.4 Disclaimer
• 4. AVR CPU Core
  • 4.1 Introduction
  • 4.2 Architectural Overview
  • 4.3 ALU – Arithmetic Logic Unit
  • 4.4 Status Register
    • 4.4.1 SREG - AVR Status Register
  • 4.5 General Purpose Register File
    • 4.5.1 The X-register, Y-register, and Z-register
  • 4.6 Stack Pointer
    • 4.6.1 SPH and SPL — Stack Pointer Register
  • 4.7 Instruction Execution Timing
  • 4.8 Reset and Interrupt Handling
    • 4.8.1 Interrupt Response Time
• 5. Memories
  • 5.1 Overview
  • 5.2 In-System Re-programmable Flash Program Memory
  • 5.3 SRAM Data Memory
    • 5.3.1 Data Memory Access Times
  • 5.4 EEPROM Data Memory
    • 5.4.1 EEPROM Read/Write Access
    • 5.4.2 Atomic Byte Programming
    • 5.4.3 Split Byte Programming
    • 5.4.4 Erase
    • 5.4.5 Write
    • 5.4.6 Preventing EEPROM Corruption
  • 5.5 I/O Memory
    • 5.5.1 General Purpose I/O Registers
  • 5.6 Register Description
    • 5.6.1 EEAR – EEPROM Address Register
    • 5.6.2 EEDR – EEPROM Data Register
    • 5.6.3 EECR – EEPROM Control Register
    • 5.6.4 GPIOR2 – General Purpose I/O Register 2
    • 5.6.5 GPIOR1 – General Purpose I/O Register 1
    • 5.6.6 GPIOR0 – General Purpose I/O Register 0
• 6. System Clock and Clock Options
  • 6.1 Clock Systems and their Distribution
    • 6.1.1 CPU Clock – clkCPU
    • 6.1.2 I/O Clock – clkI/O
    • 6.1.3 Flash Clock – clkFLASH
    • 6.1.4 ADC Clock – clkADC
  • 6.2 Clock Sources
    • 6.2.1 External Clock
    • 6.2.2 Calibrated Internal 8 MHz Oscillator
    • 6.2.3 Internal 128 kHz Oscillator
    • 6.2.4 Default Clock Source
    • 6.2.5 Clock Startup Sequence
  • 6.3 System Clock Prescaler
    • 6.3.1 Switching Time
  • 6.4 Clock Output Buffer
  • 6.5 Register Description
    • 6.5.1 OSCCAL – Oscillator Calibration Register
    • 6.5.2 CLKPR – Clock Prescale Register
• 7. Power Management and Sleep Modes
  • 7.1 Sleep Modes
    • 7.1.1 Idle Mode
    • 7.1.2 ADC Noise Reduction Mode
    • 7.1.3 Power-Down Mode
  • 7.2 Software BOD Disable
  • 7.3 Power Reduction Register
  • 7.4 Minimizing Power Consumption
    • 7.4.1 Analog to Digital Converter
    • 7.4.2 Analog Comparator
    • 7.4.3 Brown-out Detector
    • 7.4.4 Internal Voltage Reference
    • 7.4.5 Watchdog Timer
    • 7.4.6 Port Pins
  • 7.5 Register Description
    • 7.5.1 MCUCR – MCU Control Register
    • 7.5.2 PRR – Power Reduction Register
• 8. Power Supply and On-Chip Boost Converter
  • 8.1 Overview
  • 8.2 Modes of Operation
    • 8.2.1 Stop Mode
    • 8.2.2 Start Mode
    • 8.2.3 Active Mode
    • 8.2.4 Examples
  • 8.3 Output Voltage versus Load Current
    • 8.3.1 Active Regulated Mode
    • 8.3.2 Active Low Current Mode
    • 8.3.3 Full Duty Cycle
  • 8.4 Overload Behaviour
  • 8.5 Software Control of Boost Converter
    • 8.5.1 Stopping the Boost Converter
    • 8.5.2 Switching to Full Duty Cycle Mode of Operation
    • 8.5.3 Switching to Normal (Variable Duty Cycle) Mode of Operation
  • 8.6 Component Selection
    • 8.6.1 Inductor
    • 8.6.2 Diode
    • 8.6.3 Input Capacitors
    • 8.6.4 RC Filter
    • 8.6.5 Output Capacitors
    • 8.6.6 Summary
  • 8.7 Typical Applications
  • 8.8 Characteristics
  • 8.9 Potential Limitations
  • 8.10 Bypassing the Boost Converter
  • 8.11 Register Description
    • 8.11.1 ADCSRB – ADC Control and Status Register B
• 9. System Control and Reset
  • 9.1 Resetting the AVR
  • 9.2 Reset Sources
  • 9.3 Power-on Reset
  • 9.4 External Reset
  • 9.5 Brown-out Detection
  • 9.6 Watchdog Reset
  • 9.7 Internal Voltage Reference
    • 9.7.1 Voltage Reference Enable Signals and Start-up Time
  • 9.8 Watchdog Timer
    • 9.8.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
      • 9.8.1.1 Safety Level 1
      • 9.8.1.2 Safety Level 2
    • 9.8.2 Code Example
  • 9.9 Register Description
    • 9.9.1 MCUSR – MCU Status Register
    • 9.9.2 WDTCSR – Watchdog Timer Control and Status Register
• 10. Interrupts
  • 10.1 Interrupt Vectors
  • 10.2 External Interrupts
    • 10.2.1 Pin Change Interrupt Timing
  • 10.3 Register Description
    • 10.3.1 MCUCR – MCU Control Register
    • 10.3.2 GIMSK – General Interrupt Mask Register
    • 10.3.3 GIFR – General Interrupt Flag Register
    • 10.3.4 PCMSK1 – Pin Change Mask Register 1
    • 10.3.5 PCMSK0 – Pin Change Mask Register 0
• 11. I/O Ports
  • 11.1 Introduction
  • 11.2 Ports as General Digital I/O
    • 11.2.1 Configuring the Pin
    • 11.2.2 Toggling the Pin
    • 11.2.3 Switching Between Input and Output
    • 11.2.4 Reading the Pin Value
    • 11.2.5 Digital Input Enable and Sleep Modes
    • 11.2.6 Unconnected Pins
  • 11.3 Alternate Port Functions
    • 11.3.1 Alternate Functions of Port A
    • 11.3.2 Alternate Functions of Port B
  • 11.4 Register Description
    • 11.4.1 MCUCR – MCU Control Register
    • 11.4.2 PORTA – Port A Data Register
    • 11.4.3 DDRA – Port A Data Direction Register
    • 11.4.4 PINA – Port A Input Pins Address
    • 11.4.5 PORTB – Port B Data Register
    • 11.4.6 DDRB – Port B Data Direction Register
    • 11.4.7 PINB – Port BInput Pins Address
• 12. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1)
  • 12.1 Features
  • 12.2 Overview
    • 12.2.1 Registers
    • 12.2.2 Definitions
  • 12.3 Timer/Counter Clock Sources
  • 12.4 Counter Unit
  • 12.5 Output Compare Unit
    • 12.5.1 Force Output Compare
    • 12.5.2 Compare Match Blocking by TCNTn Write
    • 12.5.3 Using the Output Compare Unit
  • 12.6 Compare Match Output Unit
    • 12.6.1 Compare Output Mode and Waveform Generation
  • 12.7 Modes of Operation
    • 12.7.1 Normal Mode
    • 12.7.2 Clear Timer on Compare Match (CTC) Mode
    • 12.7.3 Fast PWM Mode
    • 12.7.4 Phase Correct PWM Mode
  • 12.8 Timer/Counter Timing Diagrams
  • 12.9 Register Description
    • 12.9.1 TCCR0A – Timer/Counter Control Register A
    • 12.9.2 TCCR1A – Timer/Counter Control Register A
    • 12.9.3 TCCR0B – Timer/Counter Control Register B
    • 12.9.4 TCCR1B – Timer/Counter Control Register B
    • 12.9.5 TCNT0 – Timer/Counter Register
    • 12.9.6 TCNT1 – Timer/Counter Register
    • 12.9.7 OCR0A – Output Compare Register A
    • 12.9.8 OCR1A – Output Compare Register A
    • 12.9.9 OCR0B – Output Compare Register B
    • 12.9.10 OCR1B – Output Compare Register B
    • 12.9.11 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
    • 12.9.12 TIMSK1 – Timer/Counter 1 Interrupt Mask Register
    • 12.9.13 TIFR0 – Timer/Counter 0 Interrupt Flag Register
    • 12.9.14 TIFR1 – Timer/Counter 1 Interrupt Flag Register
• 13. Timer/Counter Prescaler
  • 13.1 Prescaler Reset
  • 13.2 External Clock Source
  • 13.3 Register Description
    • 13.3.1 GTCCR – General Timer/Counter Control Register
• 14. USI – Universal Serial Interface
  • 14.1 Features
  • 14.2 Overview
  • 14.3 Functional Descriptions
    • 14.3.1 Three-wire Mode
    • 14.3.2 SPI Master Operation Example
    • 14.3.3 SPI Slave Operation Example
    • 14.3.4 Two-wire Mode
    • 14.3.5 Start Condition Detector
  • 14.4 Alternative USI Usage
    • 14.4.1 Half-Duplex Asynchronous Data Transfer
    • 14.4.2 4-Bit Counter
    • 14.4.3 12-Bit Timer/Counter
    • 14.4.4 Edge Triggered External Interrupt
    • 14.4.5 Software Interrupt
  • 14.5 Register Descriptions
    • 14.5.1 USICR – USI Control Register
    • 14.5.2 USISR – USI Status Register
    • 14.5.3 USIDR – USI Data Register
    • 14.5.4 USIBR – USI Data Buffer
• 15. Analog Comparator
  • 15.1 Analog Comparator Multiplexed Input
  • 15.2 Register Description
    • 15.2.1 ADCSRB – ADC Control and Status Register B
    • 15.2.2 ACSR – Analog Comparator Control and Status Register
    • 15.2.3 DIDR0 – Digital Input Disable Register 0
• 16. Analog to Digital Converter
  • 16.1 Features
  • 16.2 Overview
  • 16.3 ADC Operation
  • 16.4 Starting a Conversion
  • 16.5 Prescaling and Conversion Timing
  • 16.6 Changing Channel or Reference Selection
    • 16.6.1 ADC Input Channels
    • 16.6.2 ADC Voltage Reference
  • 16.7 ADC Noise Canceler
  • 16.8 Analog Input Circuitry
  • 16.9 Analog Noise Canceling Techniques
  • 16.10 ADC Accuracy Definitions
  • 16.11 ADC Conversion Result
  • 16.12 Temperature Measurement
  • 16.13 Register Description
    • 16.13.1 ADMUX – ADC Multiplexer Selection Register
    • 16.13.2 ADCSRA – ADC Control and Status Register A
    • 16.13.3 ADCL and ADCH – ADC Data Register
      • 16.13.3.1 ADLAR = 0
      • 16.13.3.2 ADLAR = 1
    • 16.13.4 ADCSRB – ADC Control and Status Register B
    • 16.13.5 DIDR0 – Digital Input Disable Register 0
• 17. debugWIRE On-chip Debug System
  • 17.1 Features
  • 17.2 Overview
  • 17.3 Physical Interface
  • 17.4 Software Break Points
  • 17.5 Limitations of debugWIRE
  • 17.6 Register Description
    • 17.6.1 DWDR – debugWire Data Register
• 18. Self-Programming the Flash
  • 18.1 Performing Page Erase by SPM
  • 18.2 Filling the Temporary Buffer (Page Loading)
  • 18.3 Performing a Page Write
  • 18.4 Addressing the Flash During Self-Programming
  • 18.5 EEPROM Write Prevents Writing to SPMCSR
  • 18.6 Reading the Fuse and Lock Bits from Software
    • 18.6.1 Reading Lock Bits from Firmware
    • 18.6.2 Reading Fuse Bits from Firmware
    • 18.6.3 Reading Device Signature Imprint Table from Firmware
  • 18.7 Preventing Flash Corruption
  • 18.8 Programming Time for Flash when Using SPM
  • 18.9 Register Description
    • 18.9.1 SPMCSR – Store Program Memory Control and Status Register
• 19. Memory Programming
  • 19.1 Program And Data Memory Lock Bits
  • 19.2 Fuse Bytes
    • 19.2.1 Latching of Fuses
  • 19.3 Device Signature Imprint Table
    • 19.3.1 Signature Bytes
    • 19.3.2 Calibration Byte
  • 19.4 Page Size
  • 19.5 Parallel Programming Parameters, Pin Mapping, and Commands
    • 19.5.1 Signal Names
  • 19.6 Parallel Programming
    • 19.6.1 Enter Programming Mode
    • 19.6.2 Considerations for Efficient Programming
    • 19.6.3 Chip Erase
    • 19.6.4 Programming the Flash
    • 19.6.5 Programming the EEPROM
    • 19.6.6 Reading the Flash
    • 19.6.7 Reading the EEPROM
    • 19.6.8 Programming the Fuse Low Bits
    • 19.6.9 Programming the Fuse High Bits
    • 19.6.10 Programming the Extended Fuse Bits
    • 19.6.11 Programming the Lock Bits
    • 19.6.12 Reading the Fuse and Lock Bits
    • 19.6.13 Reading the Signature Bytes
    • 19.6.14 Reading the Calibration Byte
  • 19.7 Serial Programming
    • 19.7.1 Serial Programming Algorithm
    • 19.7.2 Serial Programming Instruction set
• 20. Electrical Characteristics
  • 20.1 Absolute Maximum Ratings*
  • 20.2 DC Characteristics
  • 20.3 Speed Grades
  • 20.4 Clock Characteristics
    • 20.4.1 Calibrated Internal Oscillator Accuracy
    • 20.4.2 External Clock Drive
  • 20.5 System and Reset Characteristics
  • 20.6 External Interrupt Characteristics
  • 20.7 Boost Converter Characteristics
  • 20.8 ADC Characteristics – Preliminary Data
  • 20.9 Parallel Programming Characteristics
  • 20.10 Serial Programming Characteristics
• 21. Typical Characteristics – TBD
  • 21.1 Boost Converter
• 22. Register Summary
• 23. Instruction Set Summary
• 24. Ordering Information
  • 24.1 ATtiny43U
• 25. Packaging Information
  • 25.1 20M1
  • 25.2 20S2
• 26. Errata
  • 26.1 ATtiny43U
    • 26.1.1 Rev. C
    • 26.1.2 Rev. B
    • 26.1.3 Rev. A
• 27. Datasheet Revision History
  • 27.1 Rev. 8048B-03/09
  • 27.2 Rev. 8048A-02/09
• Table of Contents