5 start condition detector, Attiny43u – Rainbow Electronics ATtiny43U User Manual
Page 106
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8048B–AVR–03/09
ATtiny43U
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt
if necessary.
2.
In addition, the start detector will hold the SCL line low after the master has forced a
negative edge on this line (B). This allows the slave to wake up from sleep or complete
other tasks before setting up the USI Data Register to receive the address. This is done
by clearing the start condition flag and resetting the counter.
3.
The master set the first bit to be transferred and releases the SCL line (C). The slave
samples the data and shifts it into the USI Data Register at the positive edge of the SCL
clock.
4.
After eight bits containing slave address and data direction (read or write) have been
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
5.
When the slave is addressed, it holds the SDA line low during the acknowledgment
cycle before holding the SCL line low again (i.e., the USI Counter Register must be set
to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is
given by the master (F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
14.3.5
Start Condition Detector
The start condition detector is shown in
. The SDA line is delayed (in the range of 50
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in two-wire mode.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector works asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see
) must also be taken into consideration. Refer to the description
of the USISIF bit on
for further details.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
D Q
CLR
D Q
CLR