Hayes Microcomputer Products RCV56HCF - Manual (Page 52)

RCV56HCF PCI/CardBus Modem Designer’s Guide
ROCKWELL PROPRIETARY INFORMATION 1129 4-4
4.1.5 Ground Planes
1. In a 2-layer design, provide digital and analog ground plane areas in all unused space around and under digital and
analog circuit components (exclusive of the DAA), respective, on both sides of the board, and connect them such a
manner as to avoid small islands. Connect each ground plane area to like ground plane areas on the same side at
several points and to like ground plane areas on the opposite side through the board at several points. Connect all
modem DGND pins to the digital ground plane area and AGND pins to the analog ground plane area. Typically,
separate the collective digital ground plane area from the collective analog ground plane area by a fairly straight gap.
There should be no inroads of digital ground plane area extending into the analog ground plane area or visa versa.
2. In a 4-layer design, provide separate digital and analog ground planes covering the corresponding digital and analog
circuits (exclusive of the DAA), respectively. Connect all modem DGND pins to the digital ground plane and AGND pins
to the analog ground plane. Typically, separate the digital ground plane from the analog ground plane by a fairly straight
gap.
3. In a design which needs EMI filtering, define an additional “chassis” section adjacent to the bracket end of a plug-in
card. Most EMI components (usually ferrite beads/capacitor combinations) can be positioned in this section. Fill the
unused space with a chassis ground plane, and connect it to the metal card bracket and any connector shields/grounds.
4. Keep the current paths of separate board functions isolated, thereby reducing the current's travel distance. Separate
board functions are: host interface, display, digital (SRAM, EPROM, modem), and DAA. Power and ground for each of
these functions should be separate islands connected together at the power and ground source points only.
5. Connect grounds together at only one point, if possible, using a ferrite bead. Allow other points for grounds to be
connected together if necessary for EMI suppression.
6. Keep all ground traces as wide as possible, at least 25 mil to 50 mil.
7. Keep the traces connecting all decoupling capacitors to power and ground at their respective ICs as short and as direct
(i.e., not going through vias) as possible.
4.1.6 Crystal Circuit
1. Keep all traces and component leads connected to crystal input and output pins (i.e., XTLI and XTLO) short in order to
reduce induced noise levels and minimize any stray capacitance that could affect the crystal oscillator. Keep the XTLO
trace extremely short with no bends greater than 45 degrees and containing no vias since the XTLO pin is connected to
a fast rise time, high current driver.
2. Where a ground plane is not available, such as in a 2-layer design, tie the crystal capacitors ground paths using
separate short traces (as wide as possible) with minimum angles and vias directly to the corresponding device digital
ground pin nearest the crystal pins.
3. Connect crystal cases(s) to ground (if applicable).
4. Place a 100-ohm (typical) resistor between the XTLO pin and the crystal/capacitor node.
5. Connect crystal capacitor ground connections directly to GND pin on the modem device. Do not use common ground
plane or ground trace to route the capacitor GND pin to the corresponding modem GND pin.
4.1.7 VC_L1 and VREF Circuit
1. Provide extremely short, independent paths for VC_L1 and VREF capacitor connections.
a) Route the connection from the plus terminal of the 10
µ
F VC_L1 capacitor and one terminal of the 0.1
µ
F VC_L1
capacitor to the modem device VC_L1 pin (pin 24) using a single trace isolated from the trace to the VC_L1 pin
from the VREF capacitors (see step d).
b) Route the connection from the negative terminal of the 10
µ
F VC_L1 capacitor and the other terminal of a the 0.1
µ
F VC_L1 capacitor to a ferrite bead. The bead should typically have characteristics such as: impedance = 70
Ω
at
a frequency of 100 MHz , rated current = 200 mA, and maximum resistance = 0.5
Ω
. Connect the other bead
terminal to the AGND pin (pin 34) with a single trace.
c) Route the connection from the plus terminal of the 10
µ
F VREF capacitor and one terminal of the 0.1
µ
F VREF
capacitor to the modem device VREF pin (pin 25) with a single trace.
d) Route the connection from the negative terminal of 10
µ
F VREF capacitor and the other terminal of the 0.1
µ
F
VREF capacitor to the modem device VC_L1 pin (pin 24) with a single trace isolated from the trace to the VC_L1
pin from the VC_L1 capacitors (see step a).