FUJITSU MCP3130SS - Manual (Page 147)

7.8 Bus Sequence
C156-E228-02EN 7-45
7.8 Bus Sequence
SCSI bus phases are switched in the specified sequence according to the command
operation executed in the TARG. After a TARG has asserted the BSY signal in
the SELECTION or RESELECTION phase, the bus phase sequence other than
ATTENTION condition and RESET condition is controlled by the TARG.
All bus phases can be aborted through the RESET condition so that the BUS
FREE phase is always created. Also, any other phase can be followed by the BUS
FREE phase.
Note: The TARG can enter the BUS FREE phase in order to report an error
condition. For details, see Subsection 7.6.1.
Figure 7.21 shows the allowable bus phase sequence applied to systems without
the ARBITRATION phase and systems with the ARBITRATION phase. Figure
7.22 provides an example of bus phase sequence during single command
execution.
the ARBITRATION phase, systems with the ARBITRATION
phase, systems with the MESSAGE OUT phase, and systems
without the MESSAGE OUT phase. The generation of the
ATTENTION condition determines whether or not systems use the
MESSAGE OUT phase. If the ATTENTION condition is not
generated, the TARG assumes that the INIT is supporting only a
COMMAND COMPLETE message and the TARG operates so that
it will not use other messages in the subsequent command execution
sequence. The ATN signal status is ignored; therefore, the TARG
does not enter the MESSAGE OUT phase.