Document Outline

• CHAPTER 1 FR FAMILY OVERVIEW
  • 1.1 Features of the FR Family CPU Core
  • 1.2 Sample Configuration of an FR Family Device
  • 1.3 Sample Configuration of the FR Family CPU
• CHAPTER 2 MEMORY ARCHITECTURE
  • 2.1 FR Family Memory Space
    • 2.1.1 Direct Address Area
    • 2.1.2 Vector Table Area
  • 2.2 Bit Order and Byte Order
  • 2.3 Word Alignment
• CHAPTER 3 REGISTER DESCRIPTIONS
  • 3.1 FR Family Register Configuration
  • 3.2 General-purpose Registers
  • 3.3 Dedicated Registers
    • 3.3.1 Program Counter (PC)
    • 3.3.2 Program Status (PS)
    • 3.3.3 Table Base Register (TBR)
    • 3.3.4 Return Pointer (RP)
    • 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP)
    • 3.3.6 Multiplication/Division Register (MD)
• CHAPTER 4 RESET AND "EIT" PROCESSING
  • 4.1 Reset Processing
  • 4.2 Basic Operations in "EIT" Processing
  • 4.3 Interrupts
    • 4.3.1 User Interrupts
    • 4.3.2 Non-maskable Interrupts (NMI)
  • 4.4 Exception Processing
    • 4.4.1 Undefined Instruction Exceptions
  • 4.5 Traps
    • 4.5.1 "INT" Instructions
    • 4.5.2 "INTE" Instruction
    • 4.5.3 Step Trace Traps
    • 4.5.4 Coprocessor Not Found Traps
    • 4.5.5 Coprocessor Error Trap
  • 4.6 Priority Levels
• CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
  • 5.1 Pipeline Operation
  • 5.2 Pipeline Operation and Interrupt Processing
  • 5.3 Register Hazards
  • 5.4 Delayed Branching Processing
    • 5.4.1 Processing Non-delayed Branching Instructions
    • 5.4.2 Processing Delayed Branching Instructions
• CHAPTER 6 INSTRUCTION OVERVIEW
  • 6.1 Instruction Formats
  • 6.2 Instruction Notation Formats
• CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
  • 7.1 ADD (Add Word Data of Source Register to Destination Register)
  • 7.2 ADD (Add 4-bit Immediate Data to Destination Register)
  • 7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)
  • 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)
  • 7.5 ADDN (Add Word Data of Source Register to Destination Register)
  • 7.6 ADDN (Add Immediate Data to Destination Register)
  • 7.7 ADDN2 (Add Immediate Data to Destination Register)
  • 7.8 SUB (Subtract Word Data in Source Register from Destination Register)
  • 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)
  • 7.10 SUBN (Subtract Word Data in Source Register from Destination Register)
  • 7.11 CMP (Compare Word Data in Source Register and Destination Register)
  • 7.12 CMP (Compare Immediate Data of Source Register and Destination Register)
  • 7.13 CMP2 (Compare Immediate Data and Destination Register)
  • 7.14 AND (And Word Data of Source Register to Destination Register)
  • 7.15 AND (And Word Data of Source Register to Data in Memory)
  • 7.16 ANDH (And Half-word Data of Source Register to Data in Memory)
  • 7.17 ANDB (And Byte Data of Source Register to Data in Memory)
  • 7.18 OR (Or Word Data of Source Register to Destination Register)
  • 7.19 OR (Or Word Data of Source Register to Data in Memory)
  • 7.20 ORH (Or Half-word Data of Source Register to Data in Memory)
  • 7.21 ORB (Or Byte Data of Source Register to Data in Memory)
  • 7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)
  • 7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)
  • 7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)
  • 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)
  • 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
  • 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
  • 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
  • 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
  • 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
  • 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
  • 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)
  • 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)
  • 7.34 MUL (Multiply Word Data)
  • 7.35 MULU (Multiply Unsigned Word Data)
  • 7.36 MULH (Multiply Half-word Data)
  • 7.37 MULUH (Multiply Unsigned Half-word Data)
  • 7.38 DIV0S (Initial Setting Up for Signed Division)
  • 7.39 DIV0U (Initial Setting Up for Unsigned Division)
  • 7.40 DIV1 (Main Process of Division)
  • 7.41 DIV2 (Correction when Remainder is 0)
  • 7.42 DIV3 (Correction when Remainder is 0)
  • 7.43 DIV4S (Correction Answer for Signed Division)
  • 7.44 LSL (Logical Shift to the Left Direction)
  • 7.45 LSL (Logical Shift to the Left Direction)
  • 7.46 LSL2 (Logical Shift to the Left Direction)
  • 7.47 LSR (Logical Shift to the Right Direction)
  • 7.48 LSR (Logical Shift to the Right Direction)
  • 7.49 LSR2 (Logical Shift to the Right Direction)
  • 7.50 ASR (Arithmetic Shift to the Right Direction)
  • 7.51 ASR (Arithmetic Shift to the Right Direction)
  • 7.52 ASR2 (Arithmetic Shift to the Right Direction)
  • 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)
  • 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)
  • 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)
  • 7.56 LD (Load Word Data in Memory to Register)
  • 7.57 LD (Load Word Data in Memory to Register)
  • 7.58 LD (Load Word Data in Memory to Register)
  • 7.59 LD (Load Word Data in Memory to Register)
  • 7.60 LD (Load Word Data in Memory to Register)
  • 7.61 LD (Load Word Data in Memory to Register)
  • 7.62 LD (Load Word Data in Memory to Program Status Register)
  • 7.63 LDUH (Load Half-word Data in Memory to Register)
  • 7.64 LDUH (Load Half-word Data in Memory to Register)
  • 7.65 LDUH (Load Half-word Data in Memory to Register)
  • 7.66 LDUB (Load Byte Data in Memory to Register)
  • 7.67 LDUB (Load Byte Data in Memory to Register)
  • 7.68 LDUB (Load Byte Data in Memory to Register)
  • 7.69 ST (Store Word Data in Register to Memory)
  • 7.70 ST (Store Word Data in Register to Memory)
  • 7.71 ST (Store Word Data in Register to Memory)
  • 7.72 ST (Store Word Data in Register to Memory)
  • 7.73 ST (Store Word Data in Register to Memory)
  • 7.74 ST (Store Word Data in Register to Memory)
  • 7.75 ST (Store Word Data in Program Status Register to Memory)
  • 7.76 STH (Store Half-word Data in Register to Memory)
  • 7.77 STH (Store Half-word Data in Register to Memory)
  • 7.78 STH (Store Half-word Data in Register to Memory)
  • 7.79 STB (Store Byte Data in Register to Memory)
  • 7.80 STB (Store Byte Data in Register to Memory)
  • 7.81 STB (Store Byte Data in Register to Memory)
  • 7.82 MOV (Move Word Data in Source Register to Destination Register)
  • 7.83 MOV (Move Word Data in Source Register to Destination Register)
  • 7.84 MOV (Move Word Data in Program Status Register to Destination Register)
  • 7.85 MOV (Move Word Data in Source Register to Destination Register)
  • 7.86 MOV (Move Word Data in Source Register to Program Status Register)
  • 7.87 JMP (Jump)
  • 7.88 CALL (Call Subroutine)
  • 7.89 CALL (Call Subroutine)
  • 7.90 RET (Return from Subroutine)
  • 7.91 INT (Software Interrupt)
  • 7.92 INTE (Software Interrupt for Emulator)
  • 7.93 RETI (Return from Interrupt)
  • 7.94 Bcc (Branch Relative if Condition Satisfied)
  • 7.95 JMP:D (Jump)
  • 7.96 CALL:D (Call Subroutine)
  • 7.97 CALL:D (Call Subroutine)
  • 7.98 RET:D (Return from Subroutine)
  • 7.99 Bcc:D (Branch Relative if Condition Satisfied)
  • 7.100 DMOV (Move Word Data from Direct Address to Register)
  • 7.101 DMOV (Move Word Data from Register to Direct Address)
  • 7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)
  • 7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
  • 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)
  • 7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
  • 7.106 DMOVH (Move Half-word Data from Direct Address to Register)
  • 7.107 DMOVH (Move Half-word Data from Register to Direct Address)
  • 7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)
  • 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)
  • 7.110 DMOVB (Move Byte Data from Direct Address to Register)
  • 7.111 DMOVB (Move Byte Data from Register to Direct Address)
  • 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)
  • 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)
  • 7.114 LDRES (Load Word Data in Memory to Resource)
  • 7.115 STRES (Store Word Data in Resource to Memory)
  • 7.116 COPOP (Coprocessor Operation)
  • 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)
  • 7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)
  • 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)
  • 7.120 NOP (No Operation)
  • 7.121 ANDCCR (And Condition Code Register and Immediate Data)
  • 7.122 ORCCR (Or Condition Code Register and Immediate Data)
  • 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)
  • 7.124 ADDSP (Add Stack Pointer and Immediate Data)
  • 7.125 EXTSB (Sign Extend from Byte Data to Word Data)
  • 7.126 EXTUB (Unsign Extend from Byte Data to Word Data)
  • 7.127 EXTSH (Sign Extend from Byte Data to Word Data)
  • 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)
  • 7.129 LDM0 (Load Multiple Registers)
  • 7.130 LDM1 (Load Multiple Registers)
  • 7.131 STM0 (Store Multiple Registers)
  • 7.132 STM1 (Store Multiple Registers)
  • 7.133 ENTER (Enter Function)
  • 7.134 LEAVE (Leave Function)
  • 7.135 XCHB (Exchange Byte Data)
• APPENDIX
  • APPENDIX A Instruction Lists
    • A.1 Symbols Used in Instruction Lists
    • A.2 Instruction Lists
  • APPENDIX B Instruction Maps
    • B.1 Instruction Map
    • B.2 "E" Format
• INDEX
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