Pin descriptions, 2 pin descriptions – FOCUS Enhancements FS453 User Manual

Page 17

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FS453/4 AND FS455/6

DATA SHEET: HARDWARE REFERENCE

5.2 Pin Descriptions

Pin

Name

FBGA

Pin

Number

PQFP

Pin

Number

Type/Value

Pin Function Description

Clocks
CLKOUT D13

56

GTL/LVCMOS
output

Pixel Clock Output. Clock to Graphics
Control Chip (GCC) clock input. Synthesized
from XTAL_IN. 0.78125 to 150 MHz range.
Supports 1.5 to 3.3 volt CMOS or GTL.

CLKIN_P E13

54

Differential
input

Pixel Clock Input Positive. Clock from
GCC’s buffered form of CLKOUT. Used to
latch input pixel data.

CLKIN_N G12

51

Differential
input

Pixel Clock Input Negative. Clock from
GCC’s buffered form of CLKOUT. Used to
latch input pixel data. For single-clocked use,
tie CLKIN_N to PREF.

XTAL_IN B10

63

LVTTL

input

Television reference Clock Input. 27 MHz
reference clock input for the video encoder for
use with either external oscillator or 27 MHz
crystal.

XTAL_OUT A11 62

LVTTL

output

Television Clock XTAL Output. Buffered
version of XTAL_IN. For use with a 27 MHz
crystal.

Global Controls
RESET_L F12

53

TTL

input

(internal pull
down)

Reset. Active Low. Resets internal state
machines and initializes default register
values.

RSVD0 N11

39

TTL

input

(internal pull
down)

Reserved. Manufacturing Test Pin. Tie to
VSS.

GPIO3-GPIO0 C1,C2,F1

3,G13

2,3,52,

50

TTL
input/output

General Purpose Input/Output. GPIO port.

Digital RGB/YCrCb Input/Outputs
P23-P0/V656

M9,N8,M8

N6,M6,N5

M5,N4,M4

N3,L1,K2

K1,J2,J1

H2,H1,G2

G1,F2,F1
E2,E1,D2

34,33,32,
29,28,27,
26,25,24,
23,18,17,
16,15,14,
13,12,11,

10,9,8,

7,6,5

GTL/TTL
input/output

Digital GTL/TTL input port. Multiplexed
digital video input. Connects to GCC's digital
video out. In 12 bit input modes, P23-P12 are
available for ITU-R BT.656 Video Output. P18-
P12 contain the video data with embedded
control codes while P21, P22, and P23 output
HSync, VSync, and Field respectively.

PREF H12

49

GTL/TTL

REF

Digital GTL/TTL Port Reference input.
Voltage threshold reference for GTL/TTL
inputs. Set to the center of the input data logic
high and low levels, but not to exceed Voltage
Reference Range (see Electrical
Characteristics on page 25).

HSYNC N9

35

GTL/TTL

I/O

Digital HSYNC VGA I/O. Connects to GCC
HSync.

VSYNC M10

36

GTL/TTL

I/O

Digital VSYNC VGA I/O. Connects to GCC
VSync.

JANUARY, 2005, VERSION 3.0

17

COPYRIGHT

©2003-4 FOCUS ENHANCEMENTS, INC.

FOCUS Enhancements Semiconductor

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