FUJITSU MB3773 - Manual (Page 19)

MB3773
19
(Continued)
EXAMPLE 8: Stopping Watch-dog Timer (Monitoring only supply voltage)
(a) Using NPN transistor
These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the
microprocessor even if the latter, used in standby mode, stops sending the clock pulse to the MB3773.
• The watch-dog timer is inhibited by clamping the C
T
terminal voltage to V
REF
.
The supply voltage is constantly monitored even while the watch-dog timer is inhibited.
For this reason, a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop
to low voltage.
Note that in application examples (a) and (b), the hold signal is inactive when the watch-dog timer is inhibited at
the time of resetting.
If the hold signal is active when tie microprocessor is reset, the solution is to add a gate, as in examples (c)
and (d).
V
CC
(5 V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
R
2
=1 k
Ω
HALT
R
1
=1 M
Ω
(b) Using PNP transistor
V CC (5 V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
R
2
=1 k
Ω
HALT
R
1
=51 k
Ω
C
T
C
T