Motorola MC9S12GC-Family - Manual (Page 70)

Device User Guide — 9S12C128DGV1/D V01.05
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changed to known start-up states. Refer to the respective module Block User Guides for register reset
states.
5.3.1 Reset Summary Table
5.3.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External
Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to Figure 1-2 to Figure 1-5 footnotes for locations of the memories depending on the operating
mode after reset.
The RAM array is not automatically initialized out of reset.
NOTE: For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins
should be configured as outputs after reset in order to avoid current drawn from
floating inputs. Refer to
Table 2-1 for affected pins.
Section 6 HCS12 Core Block Description
Consult the individual block guides for information about the HCS12 core modules, i.e. central processing
unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus
interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM).
Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods.
6.1 Device-specific information
6.1.1 PPAGE
External paging is not supported on these devices. In order to access the 16K flash blocks in the address
range $8000-$BFFF the PPAGE register must be loaded with the corresponding value for this range. Refer
to
Table 6-1 for device specific page mapping.
Table 5-2 Reset Summary
Reset Priority Source Vector
Power-on Reset 1 CRG Module $FFFE, $FFFF
External Reset 1 RESET pin $FFFE, $FFFF
Low Voltage Reset 1 VREG Module $FFFE, $FFFF
Clock Monitor Reset 2 CRG Module $FFFC, $FFFD
COP Watchdog Reset 3 CRG Module $FFFA, $FFFB