Intel ESM-2850 2047285001R - Manual (Page 29)

User’s Manual
ESM-2850 User’s Manual 29
2.4.2.1.4 Flat Panel LVDS Signals
Signal Signal Description
BIASON Controls panel contrast voltage.
DIGON Controls panel digital power.
ENBKL# Controls backlight power enable.
I
2
C_DAT, I
2
C_CLK
I
2
C interface for panel parameter EEPROM. This EERPOM is mounted on the
LVDS receiver. The data in the EEPROM allows the EXT module to automatically
set the proper timing parameters for a specific LCD panel.
2.4.2.1.5 LPC Signals
Signal Signal Description
LPC_FRAME# LPC frame indicates the start of an LPC cycle
LPC_AD[0:3] LPC multiplexed address, command and data bus
LPC_DRQ[0:1]# LPC serial DMA request
LPC_CLK LPC clock output - 33MHz nominal
LPC_SERIRQ LPC serial interrupt