IBM POWERPC 750GL - Manual (Page 205)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_05.fm.(1.2)
March 27, 2006 Memory Management
Page 205 of 377
Figure 5-9. Primary Page Table Search
(From Figure 5-10
on page 206)
Fetch PTE from PTEG
Otherwise
Perform Secondary
Page Table Search
Alignment Exception
TLB[PTE[C]] ← 1
Generate PA Using Primary Hash Function
PA ← Base PA of PTEG
PA ← PA+ 8
(Fetch Next PTE in PTEG)
Fetch PTE (64-Bits)
from PA
PTE [VSID, API, H, V] =
Segment Descriptor [VSID], EA[API], 0, 1
PTE[C] ← 1
(Update PTE[C] in
Memory)
Also Update PTE[R]
in Memory if R_Flag = 1
PTE[R] ← 1
(Update PTE[R]
in Memory)
Last PTE in PTEG
PTE[R] = 0
R_Flag = 1
Store Operation
with PTE[C] = 0
Otherwise
R_Flag = 1
PTE[R] ← 1 (Update
PTE[R] in Memory)
Primary Page
Table Search
Write PTE into
TLB
Otherwise
Secondary Page
Table Search Hit
PTE[R] = 1
dcbz Instruction
with W or I = 1
Check Memory
Protection
R_Flag = 1
PTE[R] ← 1
(Update PTE[R]
in Memory)
Otherwise
PTE[R] ← 1
R_Flag ← 1
Memory Protection
Violation
Page Table
Search Complete
Page Table
Search Complete
Other- Otherwise
Access Permitted
Access Prohibited
Otherwise