IBM POWERPC 750GL - Manual (Page 206)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 206 of 377
gx_05.fm.(1.2)
March 27, 2006
The load store unit (LSU) initiates out-of-order accesses without knowing whether it is legal to do so. There-
fore, the MMU does not perform a hardware table search due to TLB misses until the request is required by
the program flow. In these out-of-order cases, the MMU does detect protection violations and whether a dcbz
instruction specifies a page marked as write-through or cache-inhibited. The MMU also detects alignment
exceptions caused by the dcbz instruction and prevents the changed bit in the PTE from being updated erro-
neously in these cases.
If an MMU register is being accessed by an instruction in the instruction stream, the IMMU stalls for one
translation cycle to perform that operation. The sequencer serializes instructions to ensure the data correct-
ness. To update the IBATs and SRs, the sequencer classifies those operations as fetch serializing. After such
an instruction is dispatched, the instruction buffer is flushed, and the fetch stalls until the instruction
completes. However, to read from the IBATs, the operation is classified as execution serializing. As long as
the LSU ensures that all previous instructions can be executed, subsequent instructions can be fetched and
dispatched.
Figure 5-10. Secondary Page-Table-Search Flow
Page Fault (See Figure 5-10
on page 206)
Fetch PTE from PTEG
Otherwise
Generate PA Using Primary Hash Function
PA ← Base PA of PTEG
PA ← PA+ 8
(Fetch Next PTE in PTEG)
Fetch PTE (64-Bits)
from PA
PTE [VSID, API, H, V] =
Segment Descriptor [VSID], EA[API], 1, 1
Last PTE in PTEG
Secondary Page
Table Search
Otherwise
Secondary Page
Table Search Hit
ISI Exception DSI Exception
Set SRR1[1] = 1 Set DSISR[1] = 1
Instruction Access Data Access