Intel 460GX User Manual
Intel Hardware
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Table of contents
Document Outline
- 1 Introduction
- 2 Register Descriptions
- 3 System Architecture
- 4 System Address Map
- 5 Memory Subsystem
- 6 Data Integrity and Error Handling
- 7 AGP Subsystem
- 8 WXB Hot-Plug
- 8.1 IHPC Configuration Registers
- 8.1.1 Page Number List for the IHPC PCI Register Descriptions
- 8.1.2 VID: Vendor Identification Register
- 8.1.3 DID: Device Identification Register
- 8.1.4 PCICMD: PCI Command Register
- 8.1.5 PCISTS: PCI Status Register
- 8.1.6 RID: Revision Identification Register
- 8.1.7 CLASS: Class Register
- 8.1.8 CLS: Cache Line Size
- 8.1.9 MLT: Master Latency Timer Register
- 8.1.10 HDR: Header Register
- 8.1.11 Base Address
- 8.1.12 SVID: Subsystem Vendor Identification
- 8.1.13 SID: Subsystem ID
- 8.1.14 Interrupt Line
- 8.1.15 Interrupt Pin
- 8.1.16 Hot-Plug Slot Identifier
- 8.1.17 Miscellaneous Hot-Plug Configuration
- 8.1.18 Hot-Plug Features
- 8.1.19 Switch Change SERR Status
- 8.1.20 Power Fault SERR Status
- 8.1.21 Arbiter SERR Status
- 8.1.22 Memory Access Index
- 8.1.23 Memory Mapped Register Access Port
- 8.2 IHPC Memory Mapped Registers
- 8.2.1 Page Number List for IHPC Memory Mapped Register Descriptions
- 8.2.2 Slot Enable
- 8.2.3 Hot-Plug Miscellaneous
- 8.2.4 LED Control
- 8.2.5 Hot-Plug Interrupt Input and Clear
- 8.2.6 Hot-Plug Interrupt Mask
- 8.2.7 Serial Input Byte Data
- 8.2.8 Serial Input Byte Pointer
- 8.2.9 General Purpose Output
- 8.2.10 Hot-Plug Non-interrupt Inputs
- 8.2.11 Hot-Plug Slot Identifier
- 8.2.12 Hot-Plug Switch Interrupt Redirect Enable
- 8.2.13 Slot Power Control
- 8.2.14 Extended Hot-Plug Miscellaneous
- 8.1 IHPC Configuration Registers
- 9 IFB Register Mapping
- 10 IFB Usage Considerations
- 10.1 Usage of 1MIN Timer in Power Management
- 10.2 Usage of the SW SMI# Timer
- 10.3 CD-ROM AUTO RUN Feature of the OS
- 10.4 ACPI, SMBus, GPIO Base Address Reporting to the OS
- 10.5 Ultra DMA Configuration
- 10.5.1 UDMAC–Ultra DMA Control Register (IFB Function 1 PCI Configuration Offset 48h)
- 10.5.2 UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI Configuration Offsets 4A-4Bh)
- 10.5.3 Determining a Drive’s Transfer Rate Capabilities
- 10.5.4 Determining a Drive’s Best Ultra DMA Capability
- 10.5.5 Determining a Drive’s Best Multi Word DMA/Single Word DMA (Non-ultra DMA) Capability
- 10.5.6 IFB Timing Settings
- 10.5.7 Drive Configuration for Selected Timings
- 10.5.8 Settings Checklist
- 10.5.9 Example Configurations
- 10.5.10 Ultra DMA System Software Considerations
- 10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver Considerations
- 10.6 USB Resume Enable Bit
- 11 LPC/FWH Interface Configuration
- 11.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)
- 11.1.1 VID–Vendor Identification Register (Function 0)
- 11.1.2 DID–Device Identification Register (Function 0)
- 11.1.3 PCICMD–PCI Command Register (Function 0)
- 11.1.4 PCISTS–PCI Device Status Register (Function 0)
- 11.1.5 RID–Revision Identification Register (Function 0)
- 11.1.6 CLASSC–Class Code Register (Function 0)
- 11.1.7 HEDT–Header Type Register (Function 0)
- 11.1.8 ACPI Base Address (Function 0)
- 11.1.9 ACPI Enable (Function 0)
- 11.1.10 SCI IRQ Routing Control
- 11.1.11 BIOSEN–BIOS Enable Register (Function 0)
- 11.1.12 PIRQRC[A:D]–PIRQx Route Control Registers (Function 0)
- 11.1.13 SerIRQC–Serial IRQ Control Register (Function 0)
- 11.1.14 TOM–Top of Memory Register (Function 0)
- 11.1.15 MSTAT–Miscellaneous Status Register (Function 0)
- 11.1.16 Deterministic Latency Control Register (Function 0)
- 11.1.17 MGPIOC–Muxed GPIO Control (Function 0)
- 11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)
- 11.1.19 DDMABP–Distributed DMA Slave Base Pointer Registers (Function 0)
- 11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)
- 11.1.21 GPIO Base Address (Function 0)
- 11.1.22 GPIO Enable (Function 0)
- 11.1.23 LPC COM Decode Ranges (Function 0)
- 11.1.24 LPC FDD/LPT Decode Ranges (Function 0)
- 11.1.25 LPC Sound Decode Ranges (Function 0)
- 11.1.26 LPC Generic Decode Range (Function 0)
- 11.1.27 LPC Enables (Function 0)
- 11.2 PCI to LPC I/O Space Registers
- 11.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)
- 12 IDE Configuration
- 12.1 PCI Configuration Registers (Function 1)
- 12.2 IDE Controller Register Descriptions (PCI Function 1)
- 12.2.1 VID–Vendor Identification Register (Function 1)
- 12.2.2 DID–Device Identification Register (Function 1)
- 12.2.3 PCICMD–PCI Command Register (Function 1)
- 12.2.4 PCISTS–PCI Device Status Register (Function 1)
- 12.2.5 CLASSC–Class Code Register (Function 1)
- 12.2.6 MLT–Master Latency Timer Register (Function 1)
- 12.2.7 BMIBA–Bus Master Interface Base Address Register (Function 1)
- 12.2.8 SVID–Subsystem Vendor ID (Function 1)
- 12.2.9 SID–Subsystem ID (Function 1)
- 12.2.10 IDETIM–IDE Timing Register (Function 1)
- 12.2.11 SIDETIM–Slave IDE Timing Register (Function 1)
- 12.2.12 DMACTL–Synchronous DMA Control Register (Function 1)
- 12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1)
- 12.3 IDE Controller I/O Space Registers
- 13 Universal Serial Bus (USB) Configuration
- 13.1 PCI Configuration Registers (Function 2)
- 13.2 USB Host Controller Register Descriptions (PCI Function 2)
- 13.2.1 VID–Vendor Identification Register (Function 2)
- 13.2.2 DID–Device Identification Register (Function 2)
- 13.2.3 PCICMD–PCI Command Register (Function 2)
- 13.2.4 PCISTS–PCI Device Status Register (Function 2)
- 13.2.5 RID–Revision Identification Register (Function 2)
- 13.2.6 CLASSC–Class Code Register (Function 2)
- 13.2.7 MLT–Master Latency Timer Register (Function 2)
- 13.2.8 HEDT–Header Type Register (Function 2)
- 13.2.9 USBBA–USB I/O Space Base Address (Function 2)
- 13.2.10 SVID–Subsystem Vendor ID (Function 2)
- 13.2.11 SID–Subsystem ID (Function 2)
- 13.2.12 INTLN–Interrupt Line Register (Function 2)
- 13.2.13 INTPN–Interrupt Pin (Function 2)
- 13.2.14 Miscellaneous Control (Function 2)
- 13.2.15 SBRNUM–Serial Bus Release Number (Function 2)
- 13.2.16 LEGSUP–Legacy Support Register (Function 2)
- 13.2.17 USBREN–USB Resume Enable
- 13.3 USB Host Controller I/O Space Registers
- 13.3.1 USBCMD–USB Command Register (I/O)
- 13.3.2 USBSTS–USB Status Register (I/O)
- 13.3.3 USBINTR–USB Interrupt Enable Register (I/O)
- 13.3.4 FRNUM–Frame Number Register (I/O)
- 13.3.5 FLBASEADD–Frame List Base Address Register (I/O)
- 13.3.6 SOFMOD–Start of Frame (SOF) Modify Register (I/O)
- 13.3.7 PORTSC–Port Status and Control Register (I/O)
- 14 SM Bus Controller Configuration
- 14.1 SM Bus Configuration Registers (Function 3)
- 14.2 System Management Register Descriptions
- 14.2.1 VID–Vendor Identification Register (Function 3)
- 14.2.2 DID–Device Identification Register (Function 3)
- 14.2.3 PCICMD–PCI Command Register (Function 3)
- 14.2.4 PCISTS–PCI Device Status Register (Function 3)
- 14.2.5 RID–Revision Identification Register (Function 3)
- 14.2.6 CLASSC–Class Code Register (Function 3)
- 14.2.7 SMBBA–SMBus Base Address (Function 3)
- 14.2.8 SVID–Subsystem Vendor ID (Function 3)
- 14.2.9 SID–Subsystem ID (Function 3)
- 14.2.10 INTLN–Interrupt Line Register (Function 3)
- 14.2.11 INTPN–Interrupt Pin (Function 3)
- 14.2.12 Host Configuration
- 14.2.13 smbslvc–SMBus Slave Command (Function 3)
- 14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3)
- 14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3)
- 14.3 SMBus I/O Space Registers
- 14.3.1 smbhststs–SMBus Host Status Register (I/O)
- 14.3.2 smbslvsts–SMBus Slave Status Register (I/O)
- 14.3.3 smbhstcnt–SMBus Host Control Register (I/O)
- 14.3.4 smbhstcmd–SMBus Host Command Register (I/O)
- 14.3.5 smbhstadd–SMBus Host Address Register (I/O)
- 14.3.6 smbhstdat0–SMBus Host Data 0 Register (I/O)
- 14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)
- 14.3.8 smbblkdat–SMBus Block Data Register (I/O)
- 14.3.9 smbslvcnt–SMBus Slave Control Register (I/O)
- 14.3.10 smbslvdat–SMBus Slave Data Register (I/O)
- 15 PCI/LPC Bridge Description
- 16 IFB Power Management