Intel GA-8IPXDR-E - Manual (Page 67)

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Appendix
Pin Definition Pin Definition
1 EMP Port ENABLE 36 POWER BUTTON OUT
2 5VSB 37 POWER BUTTON IN
3 SERIAL PORT 38 SYSTEM S5
4 SERIAL PORT 39 SERIAL PORT
5 SERIAL PORT 40 RESET BUTTON IN
6 SERIAL PORT 41 BUZZER STOP
7 POWER OK 42 GND
8 GND 43 CPU0 PRESENT
9 MAIN SMBUS DATA 44 CPU0 THER TRIP-
10 MAIN SMBUS CLK 45 CPU1 PRESENT
11 MAIN SMBUS ALERT 46 CPU1 THER TRIP-
12 P1 SMBUS ALERT 47 LPC LDRQ0
13 P1 SMBUS DATA 48 BMC BEEP
14 P1 SMBUS CLK 49 VCC3
15 AOL SMBUS DATA 50 VCC
16 AOL SMBUS CLK 51 BSP TRI-STATE
17 AOL SMBUS ALERT 52 ID BUTTON
18 IPMB SMBUS ALERT 53 AP TRI-STATE
19 IPMB SMBUS DATA 54 VGA FUSE
20 IPMB SMBUS CLK 55 KB/MS FUSE
21 GND 56 SCSI1 FUSE
22 BMC LPC CLOCK 57 USB1 FUSE
23 LPC FRAME 58 SCSI2 FUSE
24 GND 59 USB2 FUSE
25 LPC LAD3 60 GND
26 LPC LAD42 61 ALL ERROR LED
27 GND 62 BMC RESET OUT
28 LPC LAD1 63 HDD ERROR LED
29 LPC LAD0 64 POWER SUPPLY ERROR LED
30 3VSB 65 FAN ERROR LED
31 LPC RESET 66 SYSTEM POWER LED
32 SYSTEM NMI 67 SERIAL PORT
33 SERIAL IRQ 68 SERIAL PORT
34 GREEN OUTPUT 69 CPU0 IERR-SIGNAL
35 RESET BUTTON OUT 70 CPU1 IERR-SIGNAL
Appendix G: IPMI Connector Pin Definition