Spe programming documents, Spu instruction set architecture – Sony VERSION 1.0 User Manual

Page 14

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Guide to Cell/B.E. Programming Documentation

Version 1.0, August 2008

© 2008 Sony Computer Entertainment Inc. All Rights Reserved.

Page 14 of 16

SPE Programming Documents

SPU Instruction Set Architecture

Cell Broadband Engine Public Information and Downloads

http://cell.scei.co.jp/e_download.html

Length

278 pages.

Audience

Assembly-language programmers writing application or system programs for the SPE.

Content

The instruction set architecture (ISA) implemented by the SPEs, including descriptions of instruction functions,
instruction and data formats, interrupts, and storage-access synchronization.

Recommended Use

Browse after readings of the

CBE Programming Handbook

and refer to it thereafter as needed during coding of SPE

applications.

Document Sections

The document has the following sections:

1. Introduction: Summarizes the SPU ISA.

2. SPU Architectural Overview: Descriptions of the instruction and data formats.

3. Memory – Load/Store Instructions: Descriptions of the load, store, and generate-controls instructions.

4. Constant-Formation Instructions: Descriptions of the immediate-load instructions.

5. Integer and Logical Instructions: Descriptions of the integer, logical, count, form-select, gather, select-bits, shuffle-

bytes, and related instructions.

6. Shift and Rotate Instructions: Descriptions of the shift and rotate instructions.

7. Compare, Branch, and Halt Instructions: Descriptions of the compare, branch, and halt instructions.

8. Hint-for-Branch Instructions: Descriptions of the hint-for-branch instructions.

9. Floating-Point Instructions: Descriptions of the floating-point instructions.

10. Control Instructions: Descriptions of the control instructions, including stop-and-signal, synchronize, and move

to/from special-purpose register (SPR).

11. Channel Instructions: Descriptions of the channel read and write instructions.

12. SPU Interrupt Facility: Descriptions of the interrupt facility.

13. Synchronization and Ordering: Descriptions of the storage-access synchronization and ordering facilities.

Recommended Prerequisites

Read or browse:

ƒ

CBE Programming Handbook

ƒ

C/C++ Language Extensions for CBE Architecture

Further Details

See:

ƒ

SPU Assembly Language Specification

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