LSI 53C875A - Manual (Page 20)

1-6 General Description
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Supports additional arithmetic capability with the Expanded Register
Move instruction.
1.4.2 PCI Performance
To improve PCI performance, the LSI53C875A:
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Complies with PCI 2.2 specification.
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Supports 32-bit 33 MHz PCI interface with 64-bit addressing.
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Supports dual address cycles which can be generated for all
SCRIPTS for > 4 Gbyte addressability.
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Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.
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Supports 32-bit word data bursts with variable burst lengths.
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Prefetches up to 8 Dwords of SCRIPTS instructions.
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Bursts SCRIPTS opcode fetches across the PCI bus.
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Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz).
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Supports PCI Cache Line Size register.
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Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
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Complies with PCI Bus Power Management Specification Rev 1.1.
1.4.3 Integration
Features of the LSI53C875A which ease integration include:
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High-performance SCSI core.
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Integrated SE transceivers.
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Full 32-bit PCI DMA bus master.
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Integrated SCRIPTS processor.
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Memory-to-Memory Move instructions allow use as a third party PCI
bus DMA controller.
1.4.4 Ease of Use
The LSI53C875A provides: