LSI 53C875A - Manual (Page 316)

IX-6 Index
IDSEL 2-3 , 3-6
signal 2-5
illegal instruction detected (IID) 4-40 , 4-69
immediate
arbitration (IARB) 4-24
data 5-23
indirect addressing 5-6
initialization device select 3-6
initiator
mode 5-16
phase mismatch 4-76
ready 3-6
input 3-3
capacitance 6-2
instruction
address (IA) 4-107
block move 5-6
prefetch unit flushing 2-21
type 5-36
block move 5-6
I/O instruction 5-14
memory move 5-33
read/write instruction 5-22
transfer control instruction 5-26
internal
SCRIPTS RAM 2-18
internal RAM
see also SCRIPTS
RAM 2-18
interrupt
acknowledge command 2-4
handling 2-37
instruction 5-28
line (IL) 4-13
on-the-fly 5-30
on-the-fly (INTF) 4-49
on-the-fly instruction 5-28
output 6-10
pin (IP) 4-14
request 2-37 , 3-8
signals 3-8
status one (ISTAT1) 4-51
status zero (ISTAT0) 4-48
interrupts 2-39
fatal vs. nonfatal interrupts 2-39
halting 2-42
IRQ disable bit 2-39
masking 2-40
sample interrupt service routine 2-43
stacked interrupts 2-41
IRDY/ 3-6
IRQ
disable (IRQD) 4-72
mode (IRQM) 4-71
IRQ/ 2-37 , 3-8
pin 2-40 , 2-43
issuing cache commands 2-10
ISTAT 2-37 , 2-43
J
JTAG boundary scan testing 2-23
jump
address 5-32
call a relative address 5-29
call an absolute address 5-29
control (PMJCTL) 4-95
if true/false 5-30
instruction 5-26
L
last disconnect (LDSC) 4-47
latched SCSI parity
(SDP0L) 4-45
for SD[15:8] (SPL1) 4-47
latency 2-9
timer (LT) 4-8
LED_CNTL (LEDC) 4-83
load and store instructions 2-22 , 5-37
prefetch unit and store instructions 2-22
loopback enable 2-23
lost arbitration (LOA) 4-43
LSI53C700 compatibility (COM) 4-72
LSI53C875A
new features 1-3
M
MAC/_TESTOUT 3-11
MAD
bus 2-49
bus programming 3-14
pins 2-49
MAD[0] 3-15
MAD[3:1] 3-14
MAD[6:4] 3-14
MAD[7:0] 3-12 , 3-14
MAD[7] 3-14
mailbox one (MBOX1) 4-52
mailbox zero (MBOX0) 4-52
manual start mode (MAN) 4-68
MAS0/ 3-11
MAS1/ 3-11
masking 2-40
master
control for set or reset pulses (MASR) 4-61
data parity error (MDPE) 4-40 , 4-69
enable (ME) 4-82
parity error enable (MPEE) 4-59
max SCSI synchronous offset (MO[4:0]) 4-33
Max_Lat (ML) 4-14
maximum stress ratings 6-2
MCE/ 3-11
memory
access control 3-11
(MACNTL) 4-81
address strobe 0 3-11
address strobe 1 3-11
address/data bus 3-12
chip enable 3-11
I/O address/DSA offset 5-37
move 2-9
move instructions 2-21 , 5-32
no flush option 2-21
move read selector (MMRS) 4-100
move write selector (MMWS) 4-101
output enable 3-11
read 2-10 , 2-11
read caching 2-11
read command 2-5
read line 2-10 , 2-11