LSI 53C875A - Manual (Page 22)

1-8 General Description
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SCSI clock quadrupler bits enable Ultra SCSI transfer rates with a 20
or 40 MHz SCSI clock input.
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Selectable IRQ pin disable bit.
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Ability to route system clock to SCSI clock.
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Compatible with 3.3 V and 5 V PCI.
1.4.6 Reliability
Enhanced reliability features of the LSI53C875A include:
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2 kV ESD protection on SCSI signals.
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Protection against bus reflections due to impedance mismatches.
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Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification).
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Latch-up protection greater than 150 mA.
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Voltage feed-through protection (minimum leakage current through
SCSI pads).
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High proportion (> 25%) of device pins are power or ground.
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Power and ground isolation of I/O pads and internal chip logic.
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TolerANT technology, which provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
– Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
1.4.7 Testability
The LSI53C875A provides improved testability through:
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Access to all SCSI signals through programmed I/O.
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SCSI loopback diagnostics.
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SCSI bus signal continuity checking.
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Support for single step mode operation.
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JTAG boundary scan.