NEC PD17062 - Manual (Page 173)

173
µ
PD17062
14.3 CE RESET
CE reset is executed by raising the CE pin from low level to high level.
When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization
with the rising edge of the pulse used for the next setting of the timer carry FF.
When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some
control registers to their initial value and executes the program from address 0000H.
For the initial values, see the relevant item.
CE reset operation is different when clock-stop is used and when it is not used.
These operations are described in Sections 14.3.1 and 14.3.2, respectively.
Section 14.3.3 describes the cautions at CE reset.
14.3.1 CE Reset When Clock-Stop (STOP Instruction) Not Used
Fig. 14-2 shows the reset operation.
When clock-stop (STOP instruction) is not used, the timer mode selection register of the control registers
is not initialized.
Therefore, after the CE pin becomes high level, the RESET signal is output, and reset is applied at the rising
edge of the timer carry FF set pulse (5 or 100 ms) .
Fig. 14-2 CE Reset Operation When Clock-Stop Not Used
5 V
0 V
Normal operation
Normal
operation
X
OUT
V
DD
CE
Timer carry FF
set pulse
IRES
RES
RESET
Reset signal
CE reset is applied at the rising
edge of the timer carry FF set pulse.
This period, t, varies with the timing when
the CE pin signal rises. It falls in the range
from 0 to t
SET
(0 < t < t
SET
), which is the
selected set time of the timer carry FF .
The program continues to run during this
period.
"H"
"H"