Document Outline

• Cover
• Keep safety first in your circuit designs!
• Notes regarding these materials
• General Precautions on Handling of Product
• Important Notice on the Quality Assurance for this LSI
• Configuration of This Manual
• Preface
• Contents
• Figures
• Tables
• Section 1 Overview
  • 1.1 Features
  • 1.2 Block Diagram
  • 1.3 Pin Assignments
  • 1.4 Pin functions
• Section 2 CPU
  • 2.1 Registers
    • 2.1.1 General Registers
    • 2.1.2 Control Registers
    • 2.1.3 System Registers
    • 2.1.4 DSP Registers
  • 2.2 Data Formats
    • 2.2.1 Register Data Format (Non-DSP Type)
    • 2.2.2 DSP-Type Data Formats
    • 2.2.3 Memory Data Formats
  • 2.3 Features of CPU Core Instructions
  • 2.4 Instruction Formats
    • 2.4.1 CPU Instruction Addressing Modes
    • 2.4.2 DSP Data Addressing
    • 2.4.3 CPU Instruction Formats
    • 2.4.4 DSP Instruction Formats
  • 2.5 Instruction Set
    • 2.5.1 CPU Instruction Set
  • 2.6 DSP Extended-Function Instructions
    • 2.6.1 Introduction
    • 2.6.2 Added CPU System Control Instructions
    • 2.6.3 Single and Double Data Transfer for DSP Data Instructions
    • 2.6.4 DSP Operation Instruction Set
• Section 3 DSP Operation
  • 3.1 Data Operations of DSP Unit
    • 3.1.1 ALU Fixed-Point Operations
    • 3.1.2 ALU Integer Operations
    • 3.1.3 ALU Logical Operations
    • 3.1.4 Fixed-Point Multiply Operation
    • 3.1.5 Shift Operations
    • 3.1.6 Most Significant Bit Detection Operation
    • 3.1.7 Rounding Operation
    • 3.1.8 Overflow Protection
    • 3.1.9 Data Transfer Operation
    • 3.1.10 Local Data Move Instruction
    • 3.1.11 Operand Conflict
  • 3.2 DSP Addressing
    • 3.2.1 DSP Repeat Control
    • 3.2.2 DSP Data Addressing
• Section 4 Clock Pulse Generator (CPG)
  • 4.1 Features
  • 4.2 Input/Output Pins
  • 4.3 Clock Operating Modes
  • 4.4 Register Descriptions
    • 4.4.1 Frequency Control Register (FRQCR)
  • 4.5 Changing the Frequency
    • 4.5.1 Changing the Multiplication Rate
    • 4.5.2 Changing the Division Ratio
  • 4.6 Notes on Board Design
• Section 5 Watchdog Timer (WDT)
  • 5.1 Features
  • 5.2 Register Descriptions
    • 5.2.1 Watchdog Timer Counter (WTCNT)
    • 5.2.2 Watchdog Timer Control/Status Register (WTCSR)
    • 5.2.3 Notes on Register Access
  • 5.3 Use of the WDT
    • 5.3.1 Canceling Standbys
    • 5.3.2 Changing the Frequency
    • 5.3.3 Using Watchdog Timer Mode
    • 5.3.4 Using Interval Timer Mode
  • 5.4 Precautions to Take when Using the WDT
• Section 6 Power-Down Modes
  • 6.1 Features
    • 6.1.1 Power-Down Modes
    • 6.1.2 Reset
    • 6.1.3 Input/Output Pins
  • 6.2 Register Descriptions
    • 6.2.1 Standby Control Register (STBCR)
    • 6.2.2 Standby Control Register 2 (STBCR2)
    • 6.2.3 Standby Control Register 3 (STBCR3)
    • 6.2.4 Standby Control Register 4 (STBCR4)
  • 6.3 Operation
    • 6.3.1 Sleep Mode
    • 6.3.2 Standby Mode
    • 6.3.3 Module Standby Function
    • 6.3.4 STATUS Pin Change Timings
• Section 7 Cache
  • 7.1 Features
    • 7.1.1 Cache Structure
  • 7.2 Register Descriptions
    • 7.2.1 Cache Control Register 1 (CCR1)
    • 7.2.2 Cache Control Register 2 (CCR2)
  • 7.3 Cache Operation
    • 7.3.1 Searching Cache
    • 7.3.2 Read Access
    • 7.3.3 Prefetch Operation
    • 7.3.4 Write Access
    • 7.3.5 Write-Back Buffer
    • 7.3.6 Coherency of Cache and External Memory
  • 7.4 Memory-Mapped Cache
    • 7.4.1 Address Array
    • 7.4.2 Data Array
    • 7.4.3 Usage Examples
• Section 8 X/Y Memory
  • 8.1 Features
  • 8.2 X/Y Memory Access from CPU
  • 8.3 X/Y Memory Access from DSP
  • 8.4 X/Y Memory Access from DMAC
  • 8.5 Usage Note
  • 8.6 Sleep Mode
  • 8.7 Address Error
• Section 9 Exception Handling
  • 9.1 Register Descriptions
    • 9.1.1 TRAPA Exception Register (TRA)
    • 9.1.2 Exception Event Register (EXPEVT)
    • 9.1.3 Interrupt Event Register 2 (INTEVT2)
  • 9.2 Exception Handling Function
    • 9.2.1 Exception Handling Flow
    • 9.2.2 Exception Vector Addresses
    • 9.2.3 Exception Codes
    • 9.2.4 Exception Request and BL Bit (Multiple Exception Prevention)
    • 9.2.5 Exception Source Acceptance Timing and Priority
  • 9.3 Individual Exception Operations
    • 9.3.1 Resets
    • 9.3.2 General Exceptions
  • 9.4 Exception Processing While DSP Extension Function is Valid
    • 9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception
    • 9.4.2 Exception in Repeat Control Period
  • 9.5 Note on Initializing this LSI
  • 9.6 Usage Notes
• Section 10 Interrupt Controller (INTC)
  • 10.1 Features
  • 10.2 Input/Output Pins
  • 10.3 Register Descriptions
    • 10.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ)
    • 10.3.2 Interrupt Control Register 0 (ICR0)
    • 10.3.3 Interrupt Control Register 1 (ICR1)
    • 10.3.4 Interrupt Control Register 3 (ICR3)
    • 10.3.5 Interrupt Request Register 0 (IRR0)
    • 10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
    • 10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
  • 10.4 Interrupt Sources
    • 10.4.1 NMI Interrupt
    • 10.4.2 H-UDI Interrupt
    • 10.4.3 IRQ Interrupts
    • 10.4.4 On-Chip Peripheral Module Interrupts
    • 10.4.5 Interrupt Exception Handling and Priority
  • 10.5 INTC Operation
    • 10.5.1 Interrupt Sequence
    • 10.5.2 Multiple Interrupts
  • 10.6 Notes on Use
    • 10.6.1 Notes on USB Bus Power Control
    • 10.6.2 Timing to Clear an Interrupt Source
• Section 11 User Break Controller (UBC)
  • 11.1 Features
  • 11.2 Register Descriptions
    • 11.2.1 Break Address Register A (BARA)
    • 11.2.2 Break Address Mask Register A (BAMRA)
    • 11.2.3 Break Bus Cycle Register A (BBRA)
    • 11.2.4 Break Address Register B (BARB)
    • 11.2.5 Break Address Mask Register B (BAMRB)
    • 11.2.6 Break Data Register B (BDRB)
    • 11.2.7 Break Data Mask Register B (BDMRB)
    • 11.2.8 Break Bus Cycle Register B (BBRB)
    • 11.2.9 Break Control Register (BRCR)
    • 11.2.10 Execution Times Break Register (BETR)
    • 11.2.11 Branch Source Register (BRSR)
    • 11.2.12 Branch Destination Register (BRDR)
  • 11.3 Operation
    • 11.3.1 Flow of the User Break Operation
    • 11.3.2 Break on Instruction Fetch Cycle
    • 11.3.3 Break on Data Access Cycle
    • 11.3.4 Break on X/Y-Memory Bus Cycle
    • 11.3.5 Sequential Break
    • 11.3.6 Value of Saved Program Counter
    • 11.3.7 PC Trace
    • 11.3.8 Usage Examples
  • 11.4 Usage Notes
• Section 12 Bus State Controller (BSC)
  • 12.1 Features
  • 12.2 Input/Output Pins
  • 12.3 Area Overview
    • 12.3.1 Area Division
    • 12.3.2 Shadow Area
    • 12.3.3 Address Map
    • 12.3.4 Area 0 Memory Type and Memory Bus Width
  • 12.4 Register Descriptions
    • 12.4.1 Common Control Register (CMNCR)
    • 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
    • 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
    • 12.4.4 SDRAM Control Register (SDCR)
    • 12.4.5 Refresh Timer Control/Status Register (RTCSR)
    • 12.4.6 Refresh Timer Counter (RTCNT)
    • 12.4.7 Refresh Time Constant Register (RTCOR)
    • 12.4.8 Reset Wait Counter (RWTCNT)
  • 12.5 Operating Description
    • 12.5.1 Endian/Access Size and Data Alignment
    • 12.5.2 Normal Space Interface
    • 12.5.3 Access Wait Control
    • 12.5.4 CSn Assert Period Expansion
    • 12.5.5 MPX-I/O Interface
    • 12.5.6 SDRAM Interface
    • 12.5.7 Burst ROM (Clock Asynchronous) Interface
    • 12.5.8 Byte-Selection SRAM Interface
    • 12.5.9 Burst MPX-I/O Interface
    • 12.5.10 Burst ROM Interface (Clock Synchronous)
    • 12.5.11 Wait between Access Cycles
    • 12.5.12 Bus Arbitration
    • 12.5.13 Others
• Section 13 Direct Memory Access Controller (DMAC)
  • 13.1 Features
  • 13.2 Input/Output Pins
  • 13.3 Register Descriptions
    • 13.3.1 DMA Source Address Registers (SAR)
    • 13.3.2 DMA Destination Address Registers (DAR)
    • 13.3.3 DMA Transfer Count Registers (DMATCR)
    • 13.3.4 DMA Channel Control Registers (CHCR)
    • 13.3.5 DMA Operation Register (DMAOR)
    • 13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)
  • 13.4 Operation
    • 13.4.1 DMA Transfer Flow
    • 13.4.2 DMA Transfer Requests
    • 13.4.3 Channel Priority
    • 13.4.4 DMA Transfer Types
    • 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
    • 13.4.6 Completion of DMA Transfer
    • 13.4.7 Notes on Usage
    • 13.4.8 Notes On DREQ Sampling When DACK is Divided in External Access
• Section 14 U Memory
  • 14.1 Features
  • 14.2 U Memory Access from CPU
  • 14.3 U Memory Access from DSP
  • 14.4 U Memory Access from DMAC
  • 14.5 Usage Note
  • 14.6 Sleep Mode
  • 14.7 Address Error
• Section 15 User Debugging Interface (H-UDI)
  • 15.1 Features
  • 15.2 Input/Output Pins
  • 15.3 Register Descriptions
    • 15.3.1 Bypass Register (SDBPR)
    • 15.3.2 Instruction Register (SDIR)
    • 15.3.3 Boundary Scan Register (SDBSR)
    • 15.3.4 ID Register (SDID)
  • 15.4 Operation
    • 15.4.1 TAP Controller
    • 15.4.2 Reset Configuration
    • 15.4.3 TDO Output Timing
    • 15.4.4 H-UDI Reset
    • 15.4.5 H-UDI Interrupt
  • 15.5 Boundary Scan
    • 15.5.1 Supported Instructions
    • 15.5.2 Points for Attention
  • 15.6 Usage Notes
• Section 16 I2C Bus Interface 2 (IIC2)
  • 16.1 Features
  • 16.2 Input/Output Pins
  • 16.3 Register Descriptions
    • 16.3.1 I2C Bus Control Register 1 (ICCR1)
    • 16.3.2 I2C Bus Control Register 2 (ICCR2)
    • 16.3.3 I2C Bus Mode Register (ICMR)
    • 16.3.4 I2C Bus Interrupt Enable Register (ICIER)
    • 16.3.5 I2C Bus Status Register (ICSR)
    • 16.3.6 Slave Address Register (SAR)
    • 16.3.7 I2C Bus Transmit Data Register (ICDRT)
    • 16.3.8 I2C Bus Receive Data Register (ICDRR)
    • 16.3.9 I2C Bus Shift Register (ICDRS)
    • 16.3.10 NF2CYC Register (NF2CYC)
  • 16.4 Operation
    • 16.4.1 I2C Bus Format
    • 16.4.2 Master Transmit Operation
    • 16.4.3 Master Receive Operation
    • 16.4.4 Slave Transmit Operation
    • 16.4.5 Slave Receive Operation
    • 16.4.6 Clocked Synchronous Serial Format
    • 16.4.7 Noise Filter
    • 16.4.8 Example of Use
  • 16.5 Interrupt Request
  • 16.6 Bit Synchronous Circuit
  • 16.7 Usage Note
• Section 17 Compare Match Timer (CMT)
  • 17.1 Features
  • 17.2 Register Descriptions
    • 17.2.1 Compare Match Timer Start Register (CMSTR)
    • 17.2.2 Compare Match Timer Control/Status Register (CMCSR)
    • 17.2.3 Compare Match Counter (CMCNT )
    • 17.2.4 Compare Match Constant Register (CMCOR)
  • 17.3 Operation
    • 17.3.1 Interval Count Operation
    • 17.3.2 CMCNT Count Timing
  • 17.4 Compare Matches
    • 17.4.1 Timing of Compare Match Flag Setting
    • 17.4.2 DMA Transfer Requests and Interrupt Requests
    • 17.4.3 Timing of Compare Match Flag Clearing
• Section 18 Multi-Function Timer Pulse Unit (MTU)
  • 18.1 Features
  • 18.2 Input/Output Pins
  • 18.3 Register Descriptions
    • 18.3.1 Timer Control Register (TCR)
    • 18.3.2 Timer Mode Register (TMDR)
    • 18.3.3 Timer I/O Control Register (TIOR)
    • 18.3.4 Timer Interrupt Enable Register (TIER)
    • 18.3.5 Timer Status Register (TSR)
    • 18.3.6 Timer Counter (TCNT)
    • 18.3.7 Timer General Register (TGR)
    • 18.3.8 Timer Start Register (TSTR)
    • 18.3.9 Timer Synchro Register (TSYR)
    • 18.3.10 Timer Output Master Enable Register (TOER)
    • 18.3.11 Timer Output Control Register (TOCR)
    • 18.3.12 Timer Gate Control Register (TGCR)
    • 18.3.13 Timer Subcounter (TCNTS)
    • 18.3.14 Timer Dead Time Data Register (TDDR)
    • 18.3.15 Timer Period Data Register (TCDR)
    • 18.3.16 Timer Period Buffer Register (TCBR)
    • 18.3.17 Bus Master Interface
  • 18.4 Operation
    • 18.4.1 Basic Functions
    • 18.4.2 Synchronous Operation
    • 18.4.3 Buffer Operation
    • 18.4.4 Cascaded Operation
    • 18.4.5 PWM Modes
    • 18.4.6 Phase Counting Mode
    • 18.4.7 Reset-Synchronized PWM Mode
    • 18.4.8 Complementary PWM Mode
  • 18.5 Interrupts
    • 18.5.1 Interrupts and Priority
    • 18.5.2 DMA Activation
    • 18.5.3 A/D Converter Activation
  • 18.6 Operation Timing
    • 18.6.1 Input/Output Timing
    • 18.6.2 Interrupt Signal Timing
  • 18.7 Usage Notes
    • 18.7.1 Module Standby Mode Setting
    • 18.7.2 Input Clock Restrictions
    • 18.7.3 Caution on Period Setting
    • 18.7.4 Conflict between TCNT Write and Clear Operations
    • 18.7.5 Conflict between TCNT Write and Increment Operations
    • 18.7.6 Conflict between TGR Write and Compare Match
    • 18.7.7 Conflict between Buffer Register Write and Compare Match
    • 18.7.8 Conflict between TGR Read and Input Capture
    • 18.7.9 Conflict between TGR Write and Input Capture
    • 18.7.10 Conflict between Buffer Register Write and Input Capture
    • 18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection
    • 18.7.12 Counter Value during Complementary PWM Mode Stop
    • 18.7.13 Buffer Operation Setting in Complementary PWM Mode
    • 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
    • 18.7.15 Overflow Flags in Reset Sync PWM Mode
    • 18.7.16 Conflict between Overflow/Underflow and Counter Clearing
    • 18.7.17 Conflict between TCNT Write and Overflow/Underflow
    • 18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode
    • 18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
    • 18.7.20 Interrupts in Module Standby Mode
    • 18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection
  • 18.8 MTU Output Pin Initialization
    • 18.8.1 Operating Modes
    • 18.8.2 Reset Start Operation
    • 18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc.
    • 18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc.
  • 18.9 Port Output Enable (POE)
    • 18.9.1 Features
    • 18.9.2 Pin Configuration
    • 18.9.3 Register Configuration
    • 18.9.4 Operation
• Section 19 Serial Communication Interface with FIFO (SCIF)
  • 19.1 Overview
    • 19.1.1 Features
  • 19.2 Pin Configuration
  • 19.3 Register Description
    • 19.3.1 Receive Shift Register (SCRSR)
    • 19.3.2 Receive FIFO Data Register (SCFRDR)
    • 19.3.3 Transmit Shift Register (SCTSR)
    • 19.3.4 Transmit FIFO Data Register (SCFTDR)
    • 19.3.5 Serial Mode Register (SCSMR)
    • 19.3.6 Serial Control Register (SCSCR)
    • 19.3.7 Serial Status Register (SCFSR)
    • 19.3.8 Bit Rate Register (SCBRR)
    • 19.3.9 FIFO Control Register (SCFCR)
    • 19.3.10 FIFO Data Count Register (SCFDR)
    • 19.3.11 Serial Port Register (SCSPTR)
    • 19.3.12 Line Status Register (SCLSR)
  • 19.4 Operation
    • 19.4.1 Overview
    • 19.4.2 Operation in Asynchronous Mode
    • 19.4.3 Synchronous Operation
  • 19.5 SCIF Interrupts and DMAC
  • 19.6 Usage Notes
• Section 20 USB Function Module
  • 20.1 Features
    • 20.1.1 Block Diagram
  • 20.2 Pin Configuration
  • 20.3 Register Descriptions
    • 20.3.1 USB Interrupt Flag Register 0 (USBIFR0)
    • 20.3.2 USB Interrupt Flag Register 1 (USBIFR1)
    • 20.3.3 USB Interrupt Flag Register 2 (USBIFR2)
    • 20.3.4 USB Interrupt Select Register 0 (USBISR0)
    • 20.3.5 USB Interrupt Select Register 1 (USBISR1)
    • 20.3.6 USB Interrupt Enable Register 0 (USBIER0)
    • 20.3.7 USB Interrupt Enable Register 1 (USBIER1)
    • 20.3.8 USB Interrupt Enable Register 2 (USBIER2)
    • 20.3.9 USBEP0i Data Register (USBEPDR0i)
    • 20.3.10 USBEP0o Data Register (USBEPDR0o)
    • 20.3.11 USBEP0s Data Register (USBEPDR0s)
    • 20.3.12 USBEP1 Data Register (USBEPDR1)
    • 20.3.13 USBEP2 Data Register (USBEPDR2)
    • 20.3.14 USBEP3 Data Register (USBEPDR3)
    • 20.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o)
    • 20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)
    • 20.3.17 USB Trigger Register (USBTRG)
    • 20.3.18 USB Data Status Register (USBDASTS)
    • 20.3.19 USBFIFO Clear Register (USBFCLR)
    • 20.3.20 USBDMA Transfer Setting Register (USBDMAR)
    • 20.3.21 USB Endpoint Stall Register (USBEPSTL)
    • 20.3.22 USB Transceiver Control Register (USBXVERCR)
    • 20.3.23 USB Bus Power Control Register (USBCTRL)
  • 20.4 Operation
    • 20.4.1 Cable Connection
    • 20.4.2 Cable Disconnection
    • 20.4.3 Control Transfer
    • 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs)
    • 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs)
    • 20.4.6 EP3 Interrupt-IN Transfer
  • 20.5 Processing of USB Standard Commands and Class/Vendor Commands
    • 20.5.1 Processing of Commands Transmitted by Control Transfer
  • 20.6 Stall Operations
    • 20.6.1 Forcible Stall by Application
    • 20.6.2 Automatic Stall by USB Function Module
  • 20.7 DMA Transfer
    • 20.7.1 DMA Transfer for Endpoint 1
    • 20.7.2 DMA Transfer for Endpoint 2
  • 20.8 Example of USB External Circuitry
  • 20.9 USB Bus Power Control Method
    • 20.9.1 USB Bus Power Control Operation
    • 20.9.2 Usage Example of USB Bus Power Control Method
  • 20.10 Notes on Usage
    • 20.10.1 Receiving Setup Data
    • 20.10.2 Clearing FIFO
    • 20.10.3 Overreading or Overwriting Data Register
    • 20.10.4 Assigning Interrupt Source for EP0
    • 20.10.5 Clearing FIFO when Setting DMA Transfer
    • 20.10.6 Manual Reset for DMA Transfer
    • 20.10.7 USB Clock
    • 20.10.8 Using TR Interrupt
• Section 21 A/D Converter
  • 21.1 Features
    • 21.1.1 Block Diagram
    • 21.1.2 Input Pins
    • 21.1.3 Register Configuration
  • 21.2 Register Descriptions
    • 21.2.1 A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)
    • 21.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1)
    • 21.2.3 A/D0, A/D1 Control Register (ADCR)
  • 21.3 Operation
    • 21.3.1 Single Mode
    • 21.3.2 Multi Mode
    • 21.3.3 Scan Mode
    • 21.3.4 Simultaneous Sampling Operation
    • 21.3.5 A/D Converter Activation by MTU
    • 21.3.6 Input Sampling and A/D Conversion Time
  • 21.4 Interrupt and DMAC Transfer Request
  • 21.5 Definitions of A/D Conversion Accuracy
  • 21.6 Usage Notes
    • 21.6.1 Setting Analog Input Voltage
    • 21.6.2 Processing of Analog Input Pins
    • 21.6.3 Permissible Signal Source Impedance
    • 21.6.4 Influences on Absolute Precision
    • 21.6.5 Stop during A/D Conversion
• Section 22 Pin Function Controller (PFC)
  • 22.1 Register Descriptions
    • 22.1.1 Port A Control Register (PACR)
    • 22.1.2 Port B Control Register (PBCR)
    • 22.1.3 Port C Control Register (PCCR)
    • 22.1.4 Port D Control Register (PDCR)
    • 22.1.5 Port E Control Register (PECR)
    • 22.1.6 Port E I/O Register (PEIOR)
    • 22.1.7 Port E MTU R/W Enable Register (PEMTURWER)
    • 22.1.8 Port F Control Register (PFCR)
    • 22.1.9 Port G Control Register (PGCR)
    • 22.1.10 Port H Control Register (PHCR)
    • 22.1.11 Port J Control Register (PJCR)
  • 22.2 I/O Buffer Internal Block Diagram
    • 22.2.1 I/O Buffer with Weak Keeper
    • 22.2.2 I/O Buffer with Open Drain Output
  • 22.3 Notes on Usage
• Section 23 I/O Ports
  • 23.1 Port A
    • 23.1.1 Register Description
    • 23.1.2 Port A Data Register (PADR)
  • 23.2 Port B
    • 23.2.1 Register Description
    • 23.2.2 Port B Data Register (PBDR)
  • 23.3 Port C
    • 23.3.1 Register Description
    • 23.3.2 Port C Data Register (PCDR)
  • 23.4 Port D
    • 23.4.1 Register Description
    • 23.4.2 Port D Data Register (PDDR)
  • 23.5 Port E
    • 23.5.1 Register Description
    • 23.5.2 Port E Data Register (PEDR)
  • 23.6 Port F
    • 23.6.1 Register Description
    • 23.6.2 Port F Data Register (PFDR)
  • 23.7 Port G
    • 23.7.1 Register Description
    • 23.7.2 Port G Data Register (PGDR)
    • 23.7.3 Port G Internal Block Diagram
  • 23.8 Port H
    • 23.8.1 Register Description
    • 23.8.2 Port H Data Register (PHDR)
  • 23.9 Port J
    • 23.9.1 Register Description
    • 23.9.2 Port J Data Register (PJDR)
• Section 24 List of Registers
  • 24.1 Register Addresses (by functional module, in order of the corresponding section numbers)
  • 24.2 Register Bits
  • 24.3 Register States in Each Operating Mode
• Section 25 Electrical Characteristics
  • 25.1 Absolute Maximum Ratings
    • 25.1.1 Power-On Sequence
  • 25.2 DC Characteristics
  • 25.3 AC Characteristics
    • 25.3.1 Clock Timing
    • 25.3.2 Control Signal Timing
    • 25.3.3 AC Bus Timing
    • 25.3.4 Basic Timing
    • 25.3.5 Bus Cycle of Byte-Selection SRAM
    • 25.3.6 Burst ROM Read Cycle
    • 25.3.7 Synchronous DRAM Timing
    • 25.3.8 Peripheral Module Signal Timing
    • 25.3.9 Multi Function Timer Pulse Unit Timing
    • 25.3.10 POE Module Signal Timing
    • 25.3.11 I2C Module Signal Timing
    • 25.3.12 H-UDI Related Pin Timing
    • 25.3.13 USB Module Signal Timing
    • 25.3.14 USB Transceiver Timing
    • 25.3.15 AC Characteristics Measurement Conditions
  • 25.4 A/D Converter Characteristics
• Appendix
  • A. Pin States
    • A.1 When Other Function is Selected
    • A.2 When I/O Port is Selected
  • B. Product Lineup
  • C. Package Dimensions
• Main Revisions and Additions in this Edition
• Index
• Colophon
• Address List
• Back Cover