8 l0, l1, h0 sarams, 9 boot rom – Texas Instruments TMS320F2802 User Manual
Page 35
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SPRS230N – OCTOBER 2003 – REVISED MAY 2012
3.2.8
L0, L1, H0 SARAMs
The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into three
blocks (L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided
into two blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16
of single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline
stalls. Each block is mapped to both program and data space.
3.2.9
Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
Table 3-7. Boot Mode Selection
GPIO18
GPIO29
MODE
DESCRIPTION
SPICLKA
GPIO34
SCITXDA
SCITXDB
Boot to Flash/ROM
Jump to Flash/ROM address 0x3F 7FF6
1
1
1
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
SCI-A Boot
Load a data stream from SCI-A
1
1
0
SPI-A Boot
Load from an external serial SPI EEPROM on SPI-A
1
0
1
I2C Boot
Load data from an external EEPROM at address 0x50 on
1
0
0
the I2C bus
eCAN-A Boot
Call CAN_Boot to load from eCAN-A mailbox 1.
0
1
1
Boot to M0 SARAM
Jump to M0 SARAM address 0x00 0000.
0
1
0
Boot to OTP
Jump to OTP address 0x3D 7800
0
0
1
Parallel I/O Boot
Load data from GPIO0 - GPIO15
0
0
0
Copyright © 2003–2012, Texas Instruments Incorporated
Functional Overview
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