Document Outline

• Table of Contents
• 1 F280x, F2801x, C280x DSPs
  • 1.1 Features
  • 1.2 Getting Started
• 2 Introduction
  • 2.1 Pin Assignments
  • 2.2 Signal Descriptions
• 3 Functional Overview
  • 3.1 Memory Maps
  • 3.2 Brief Descriptions
    • 3.2.1 C28x CPU
    • 3.2.2 Memory Bus (Harvard Bus Architecture)
    • 3.2.3 Peripheral Bus
    • 3.2.4 Real-Time JTAG and Analysis
    • 3.2.5 Flash
    • 3.2.6 ROM
    • 3.2.7 M0, M1 SARAMs
    • 3.2.8 L0, L1, H0 SARAMs
    • 3.2.9 Boot ROM
    • 3.2.10 Security
    • 3.2.11 Peripheral Interrupt Expansion (PIE) Block
    • 3.2.12 External Interrupts (XINT1, XINT2, XNMI)
    • 3.2.13 Oscillator and PLL
    • 3.2.14 Watchdog
    • 3.2.15 Peripheral Clocking
    • 3.2.16 Low-Power Modes
    • 3.2.17 Peripheral Frames 0, 1, 2 (PFn)
    • 3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
    • 3.2.19 32-Bit CPU-Timers (0, 1, 2)
    • 3.2.20 Control Peripherals
    • 3.2.21 Serial Port Peripherals
  • 3.3 Register Map
  • 3.4 Device Emulation Registers
  • 3.5 Interrupts
    • 3.5.1 External Interrupts
  • 3.6 System Control
    • 3.6.1 OSC and PLL Block
      • 3.6.1.1 External Reference Oscillator Clock Option
      • 3.6.1.2 PLL-Based Clock Module
      • 3.6.1.3 Loss of Input Clock
    • 3.6.2 Watchdog Block
  • 3.7 Low-Power Modes Block
• 4 Peripherals
  • 4.1 32-Bit CPU-Timers 0/1/2
  • 4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
  • 4.3 Hi-Resolution PWM (HRPWM)
  • 4.4 Enhanced CAP Modules (eCAP1/2/3/4)
  • 4.5 Enhanced QEP Modules (eQEP1/2)
  • 4.6 Enhanced Analog-to-Digital Converter (ADC) Module
    • 4.6.1 ADC Connections if the ADC Is Not Used
    • 4.6.2 ADC Registers
  • 4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
  • 4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
  • 4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
  • 4.10 Inter-Integrated Circuit (I2C)
  • 4.11 GPIO MUX
• 5 Device Support
  • 5.1 Device and Development Support Tool Nomenclature
  • 5.2 Documentation Support
  • 5.3 Community Resources
• 6 Electrical Specifications
  • 6.1 Absolute Maximum Ratings
  • 6.2 Recommended Operating Conditions
  • 6.3 Electrical Characteristics
  • 6.4 Current Consumption
    • 6.4.1 Reducing Current Consumption
    • 6.4.2 Current Consumption Graphs
  • 6.5 Emulator Connection Without Signal Buffering for the DSP
  • 6.6 Timing Parameter Symbology
    • 6.6.1 General Notes on Timing Parameters
    • 6.6.2 Test Load Circuit
    • 6.6.3 Device Clock Table
  • 6.7 Clock Requirements and Characteristics
  • 6.8 Power Sequencing
    • 6.8.1 Power Management and Supervisory Circuit Solutions
  • 6.9 General-Purpose Input/Output (GPIO)
    • 6.9.1  GPIO - Output Timing
    • 6.9.2  GPIO - Input Timing
    • 6.9.3 Sampling Window Width for Input Signals
    • 6.9.4 Low-Power Mode Wakeup Timing
  • 6.10 Enhanced Control Peripherals
    • 6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
    • 6.10.2 Trip-Zone Input Timing
    • 6.10.3 External Interrupt Timing
    • 6.10.4 I2C Electrical Specification and Timing
    • 6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing
    • 6.10.6 SPI Slave Mode Timing
    • 6.10.7 On-Chip Analog-to-Digital Converter
      • 6.10.7.1 ADC Power-Up Control Bit Timing
      • 6.10.7.2 Definitions
      • 6.10.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
      • 6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
  • 6.11 Detailed Descriptions
  • 6.12 Flash Timing
  • 6.13 ROM Timing (C280x only)
• 7 Migrating From F280x Devices to C280x Devices
  • 7.1 Migration Issues
• 8  Revision History
• 9 Mechanical Data