Texas Instruments TMS320DM357 - Manual (Page 47)

IN token sent
?
received
STALL
No
Yes
Yes
No
RxStall set
ReqPkt cleared
Error Count cleared
Interrupt generated
Problem in
data sent
Yes
?
Data0/1
received
Transaction
complete
No
NAK
received
?
Yes
?
NAK limit
reached
No
Yes
Error count
cleared
incremented
Error count
NAK Timeout set
Endpoint halted
Interrupt generated
?
Error
count=3
No
Error bit set
ReqPkt cleared
Error Count cleared
Interrupt generated
Yes
Implies problem
at peripheral end
of connection.
Transaction deemed
complete
For each IN packet
requested in SETUP phase
ReqPkt
set
?
No
ACK sent
RxPktRdy
set
ReqPkt cleared
Error Count cleared
Interrupt generated
3.2.1.3 OUT Data Phase
www.ti.com USB Controller Host and Peripheral Modes Operation
Figure 10. IN Data Phase Flow Chart
For the OUT Data Phase of a control transaction ( Figure 11 ), the software driving the USB host device
needs to:
1. Load the data to be sent into the endpoint 0 FIFO.
2. Set the TXPKTRDY bit of HOST_CSR0 (bit 1). The controller then proceeds to send an OUT token
followed by the data from the FIFO to Endpoint 0 of the addressed device, retrying as necessary.
3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit
(bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL bit is set, it indicates that the target has issued a STALL response.
If ERROR bit is set, it means that the controller has tried to send the OUT token and the following data
packet three times without getting any response.
SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 47
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