Texas Instruments TMS320DM357 - Manual (Page 48)

For each OUT packet
specified in SETUP phase
TxPktRdy
set
?
OUT token sent
DATA0/1 packet sent
?
received
Stall
No
Yes
Yes
No
RxStall set
TxPktRdy cleared
Error Count cleared
interrupt generated
Command could
not be completed
TxPktRdy cleared
Error Count cleared
Interrupt generated
Yes
?
No
ACK
received
Transaction
complete
No
NAK
received
?
Yes
?
NAK limit
reached
No
Yes
Error count
cleared
incremented
Error count
NAK Timeout set
Endpoint halted
Interrupt generated
?
Error
count=3
No
Error bit set
TxPktRdy cleared
Error Count cleared
interrupt generated
Yes
Implies problem
at peripheral end
of connection.
Transaction deemed
complete
USB Controller Host and Peripheral Modes Operation www.ti.com
If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to
send the OUT token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT
bit.
If none of RXSTALL, ERROR or NAKLIMIT is set, the OUT data has been correctly ACKed.
4. If further data needs to be sent, the software should repeat Steps 1-3.
When all the data has been successfully sent, the software should proceed to the IN Status Phase of
the Control Transaction.
Figure 11. OUT Data Phase Flow Chart
Universal Serial Bus (USB) Controller 48 SPRUGH3 – November 2008
Submit Documentation Feedback