Xilinx PCI32 - Manual (Page 7)

PCI32 Interface v3.0
DS206 August 31, 2005 www.xilinx.com 7
Product Specification v3.0.151
Bandwidth
The PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and
receiving data. This interface supports a sustained bandwidth of up to 264 MBytes/sec. The design can
be configured to take advantage of the ability of the PCI Interface to do very long bursts.
The flexible user application interface, combined with support for many different PCI features, gives
users a solution that lends itself to use in many high-performance applications. The user is not locked
into one DMA engine; hence, an optimized design that fits a specific application can be designed.
Recommended Design Experience
The PCI Interface is pre-implemented, allowing engineering focus on the unique user application func-
tions of a PCI design. Regardless, PCI is a high-performance design that is challenging to implement in
any technology. Therefore, previous experience with building high-performance, pipelined FPGA
designs using Xilinx implementation software, constraint files, and guide files is recommended. The
challenge to implement a complete PCI design including user application functions varies depending
on configuration and functionality of your application. Contact your local Xilinx representative for a
closer review and estimation for your specific requirements.