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Virtex-5 FPGA ML561
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Xilinx Virtex-5 FPGA ML561 User Manual
User guide
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Virtex-5 FPGA ML561
Memory Interfaces
Development Board
User Guide
UG199 (v1.2.1) June 15, 2009
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Table of contents
Document Outline
Virtex-5 FPGA ML561 Memory Interfaces Development Board
Table of Contents
About This Guide
Guide Contents
Additional Documentation
Additional Support Resources
Conventions
Typographical
Online Document
Terminology
Introduction
About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
Virtex-5 FPGA ML561 Memory Interfaces Development Board
Getting Started
Documentation and Reference Design CD
Initial Board Check Before Applying Power
Applying Power to the Board
Hardware Description
Hardware Overview
FPGA
Memories
Memory Details
DDR400 and DDR2 Component Memories
DDR2 SDRAM DIMM
QDRII and RLDRAM II Memories
External Interfaces
RS-232
USB
Clocks
User I/Os
Power Regulation
Power Distribution
Voltage Regulators
Board Design Considerations
Electrical Requirements
Power Consumption
FPGA Internal Power Budget
Signal Integrity Recommendations
Termination and Transmission Line Summaries
Configuration
Configuration Modes
JTAG Chain
JTAG Port
Parallel IV Cable Port
System ACE Interface
ML561 Hardware-Simulation Correlation
Introduction
Test Setup
Signal Integrity Correlation Results
DDR2 Component Write Operation
DDR2 Component Read Operation
DDR2 DIMM Write Operation
DDR2 DIMM Read Operation
QDRII Write Operation
QDRII Read Operation
Summary and Recommendations
How to Generate a User-Specific FPGA IBIS Model
FPGA Pinouts
FPGA #1 Pinout
FPGA #2 Pinout
FPGA #3 Pinout
Bill of Materials
LCD Interface
General
Display Hardware Design
Hardware Schematic Diagram
Peripheral Device KS0713
Operation Example of the 64128EFCBC-3LP
Instruction Set
Read/Write Characteristics (6800 Mode)
Design Examples
Array Connector Numbering
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