Xilinx Virtex-5 FPGA ML561 - Manual (Page 137)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 137
UG199 (v1.2.1) June 15, 2009
Hardware Schematic Diagram R
When presenting byte value 30 hex, character 0 must be displayed. Shifting the value
00110000b (30h) up three positions gives the value 180h or 348d.
Because each character uses eight byte locations, character 0 in the character set starts from
memory location 348 decimal.
For example, character X has byte value 58h or 01011000b. Shifting this value three
positions gives the value 2C0h or 704d.
Figure C-10: Block RAM Organization
F0 - FF
The RAM array is divided in
pages of eight bytes by 16,
forming an array of 128 bytes.
This array represents one
column of standard ASCII table.
A character is stored as:
E0 - EF
D0 - DF
C0 - CF
B0 - BF
A0 - AF
Not Used
Not Used
70 - 7F
60 - 6F
50 - 5F
40 - 4F
30 - 3F
20 - 2F
10 - 1F
Not Used
2047
1280
1279
1024
1023
N-x
N
N-1 Shift
Direction
Addr
0
0 1 2 3 4 5 6 7 Data
256
255
0
Addr[10:0]
Data[7:0]
RAMB16_S9
UG199_C_10_050106