Xilinx Virtex-5 FPGA ML561 - Manual (Page 53)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 53
UG199 (v1.2.1) June 15, 2009
System ACE Interface R
Table 6-2 shows the System ACE interface signal names, descriptions, and pin
assignments.
Table 6-2: System ACE Interface Signal Descriptions
System ACE Pin Number Signal Name
70 SYSACE_MPA0
69 SYSACE_MPA1
68 SYSACE_MPA2
67 SYSACE_MPA3
45 SYSACE_MPA4
44 SYSACE_MPA5
43 SYSACE_MPA6
66 SYSACE_MPD0
65 SYSACE_MPD1
63 SYSACE_MPD2
62 SYSACE_MPD3
61 SYSACE_MPD4
60 SYSACE_MPD5
59 SYSACE_MPD6
58 SYSACE_MPD7
77 SYSACE_CTRL0/MPOE
76 SYSACE_CTRL1/MPWE
42 SYSACE_CTRL2/MPCE
41 SYSACE_CTRL3/MPIRQ
39 SYSACE_CTRL4/MPBRDY
93 SYSACE_CLK